The traditional low-pass sigma-delta ( Sigma Delta ) analog-to-digital converter is extended to the bandpass case. For input signals with small relative bandwidths, bandpass Sigma Delta converters offer high signal-to-noise ratios at significantly lower sampling rates than are required for low-pass Sigma Delta converters. A sixth-order single-ended switched-capacitor circuit, clocked at 3 MHz, is designed to convert bandpass signals centered at 455 kHz with 20-kHz bandwidth. Time-domain circuit simulations show that this modulator realizes a 94-dB signal-to-noise ratio for a half-scale input, giving roughly 16-b performance. >

Bandpass sigma-delta analog-to-digital conversion

A switching scheme for a delta-sigma modulator (DSM) is described that allows double-sampled integrators to be used without degrading the performance of the DSM. To implement double sampling, two capacitors are required and it is impossible to assure perfect matching of these capacitors. With previously described switching methods, this capacitor mismatch causes a degradation in baseband signal-to-noise ratio. The novel switching scheme converts the capacitive mismatch into an additive out-of-band tone that has no impact on the performance of the DSM. Simulations have verified that, for arbitrary capacitor mismatches with an ideal op-amp, the improved double sampling scheme provides nearly perfect performance. >

An improved double sampling scheme for switched-capacitor delta-sigma modulators

In this paper, an efficient, accurate, stable, and explicit method for transient analysis of lumped linear time invariant circuits is given. The method formulates a set of finite difference equations in the analog domain for sampled data simulation of the circuit. The solution of these equations gives the network response at fixed and equally spaced discrete instants of time. The fixed-time interval between each solution can be chosen arbitrarily and does not depend on the circuit time constants. The transient solution at each time point requires one matrix/vector multiplication and vector addition only. The algorithm is a general computer oriented formulation method that can be applied to any linear circuit. In addition to linear time invariant circuits, the method can be applied to a restricted class of time varying and/or nonlinear circuits. It is directly applicable to linear networks containing periodically clocked ideal switches, for example, switched capacitor and switched current circuits. In these networks, the circuit is linear inside each phase and changes its topology at fixed discrete instants of time. All nonlinear elements allowed in analysis must be clocked, such that their characteristics change only at discrete instants of time. For example, clocked digital circuits, such as, ideal comparators, A/D and D/A blocks are allowed. In particular, the method is applied to the simulation of oversampled delta-sigma modulators. The method can be used to study the effect of clock feed through, finite switch resistance, and finite gain bandwidth of operational amplifiers on the performance of these modulators. In addition, the algorithm can be used for analysis of continuous time delta-sigma modulators. Examples of simulation results are given.

Sampled data simulation of linear and nonlinear circuits

A software tool named TOSCA (Tool for Oversampled Switched-Capacitor A/D Converter Analysis) is described. The simulator is behavioral, general purpose and fully user-friendly. Because a set of basic building blocks is available, generic switched-capacitor noise-shaping A/D converters can be analyzed simply by building netlist file. Two hierarchical levels have been considered for circuit description: block level for subcircuits like quantizers and digital filters, and component level for subcircuits like the integrators where switches, capacitors and operational amplifiers are used as building elements. The developed models allow the most relevant nonideal parameters of the components to be taken into account, and a set of postprocessing facilities allows extensive analysis of the circuits. The program is written in C language, uses dynamic memory allocation, and is very fast. >

TOSCA: a simulator for switched-capacitor noise-shaping A/D converters

A second-order double-sampled delta-sigma modulator is described. It uses an additive-error switching scheme to convert capacitor mismatch into an additive out-of-band tone that can be removed by a digital filter. With a sampling rate of 5 MHz and an oversampling ratio of 256, the maximum measured signal-to-noise-and-distortion ratio (SNDR) is 86.3 dB, and the total harmonic distortion is -88.7 dB when the input is 2 dB below full scale. The modulator is fully differential, occupies 5 mm/sup 2/, and dissipates 13 mW.

A second-order double-sampled delta-sigma modulator using additive-error switching

The simulation of mixed switched-capacitor/digital (SC/D) networks containing capacitors, independent and linear-dependent voltage sources, switches controlled either by periodic or nonperiodic Boolean signals, latched comparators, and logic gates is considered. A unified linear switched-capacitor network (SCN) and mixed SC/D network simulator, SWITCAP2, and its applications to several widely used and novel nonlinear SCNs are discussed. The switches may be controlled by periodic waveforms and by nonperiodic waveforms from the outputs of comparators and logic gates. The signal-dependent modification of network topology through the comparators, logic gates, and signal-driven switches makes the modeling of various nonlinear switched-capacitor circuits possible. Simulation results for a pulse-code modulation (PCM) voice encoder, a sigma-delta modulator, a neural network, and a phase-locked loop (PLL) are presented to demonstrate the flexibility of the approach. >

S.-C. Fang

Papers

Simulation of mixed switched-capacitor/digital networks with signal-driven switches