The modulation of current through an electrostatically formed nanowire (EFN) is controlled by the voltage on the four input gates. The behavior of this multi-gate transistor can be interpreted as a complex four-input switching process, enabling the computation of multiple-input threshold logic functions using a single device. We have therefore created a novel threshold logic family leveraging these unique capabilities that enables the efficient computation of complex logic functions. Experimental and simulation data are provided to demonstrate feasibility and evaluate behavior. This logic family overcomes the challenge posed by the input-output voltage mismatch inherent to EFNs and produces circuits with one-eighth the number of active logic devices and one-quarter the number of transistors required by CMOS.

Threshold Logic With Electrostatically Formed Nanowires

Modeling of SOI four-gate transistor (G4FET) using multidimensional spline interpolation method

In the double-drain multistate electrostatically formed nanowire transistor (MSET), the electrostatically formed conduction channel shifts laterally by properly biasing the two side gates that enclose the bulk area. This current switching mechanism enhances functionality within a single device and sets the stage for a family of integrated-circuit building blocks that facilitate the implementation of ultralow-power Internet-of-Things applications. This paper establishes a conceptual framework for the MSET-based nand gate whose speed and power consumption are analyzed via TCAD simulations.

A Paradigm for Integrated Circuits Based on the MSET Transistor

Circuit simulation is an indispensable part of modern IC design. The significant cost of fabrication has driven researchers to verify the chip functionality through simulation before submitting the design for final fabrication. With the impending end of Moore’s Law, researchers all over the world are looking for new devices with enhanced functionality. A plethora of promising emerging devices has been proposed in recent years. In order to leverage the full potential of such devices, circuit designers need fast, reliable models for SPICE simulation to explore different applications. Most of these new devices have complex underlying physical mechanism rendering the model development an extremely challenging task. For the models to be of practical use, they have to enable fast and accurate simulation that rules out the possibility of numerically solving a system of partial differential equations to arrive at a solution. In this chapter, we show how different modeling approaches can be used to simulate three emerging semiconductor devices namely, silicononinsulator four gate transistor(GFET), perimeter gated single photon avalanche diode (PG-SPAD) and insulator-metal transistor (IMT) device with volatile memristance. All the models have been verified against experimental /TCAD data and implemented in commercial circuit simulator.

/pdf/modeling-emerging-semiconductor-devices-for-circuit-13hdmldnhv.pdf

Modeling Emerging Semiconductor Devices for Circuit Simulation

An efficient numerical model of silicon-on-insulator (SOI) four-gate transistors (G4FET) and its implementation in circuit simulator is presented here. A set of available data for different operating conditions is used to empirically determine the parameters of this model and a different set of test data is used to verify its predictive accuracy. This DC model is used to express the drain current as a single multivariate regression polynomial with its validity spanning across different possible operating regions as long as the chosen independent variables lie within the range of data set used to develop the model. The continuity of the polynomial model and its derivatives makes it particularly suitable for implementation in a circuit simulator. Models for both n-channel and p-channel G4FETs have been developed and validated using TCAD and experimental data and are successfully implemented in SPICE simulator for simulating two experimentally demonstrated G4FET circuits.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2018.0059

DC modelling of SOI four‐gate transistor (G 4 FET) for implementation in circuit simulator using multivariate regression polynomial

Novel G4-FET based logic-circuits (adjustable-threshold inverter, real-time reconfigurable logic gates and DRAM cell) are experimentally demonstrated. The independent action of the four gates helps minimize the required transistor count per logic function while enhancing design flexibility

S. Chen

Papers

Digital Circuits Using SOI Four-Gate Transistor