This survey deals with 1/f noise in homogeneous semiconductor samples. A distinction is made between mobility noise and number noise. It is shown that there always is mobility noise with an /spl alpha/ value with a magnitude in the order of 10/sup -4/. Damaging the crystal has a strong influence on /spl alpha/, /spl alpha/ may increase by orders of magnitude. Some theoretical models are briefly discussed none of them can explain all experimental results. The /spl alpha/ values of several semiconductors are given. These values can be used in calculations of 1/f noise in devices. >

1/f Noise Sources

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

Method and Apparatus Improving Gate Oxide Reliability by Controlling Accumulated Charge

We report a specific, label-free and real-time detection of femtomolar protein concentrations with a novel type of nanowire-based biosensor. The biosensor is based on an electrostatically formed nanowire, which is conceptually different from a conventional silicon nanowire in its confinement potential, charge carrier distribution, surface states, dopant distribution, moveable channel and geometrical structure. This new biosensor requires standard integrated-circuit processing with relaxed fabrication requirements. The biosensor is composed of an accumulation-type, planar transistor surrounded by four gates, a backgate, front gate and two lateral gates, and it operates in the all-around-depletion mode. Consequently, adjustment of the four gates defines the dimensions and location of the conducting channel. It is shown that lithographically shaped channels of 400 nm in width are reduced to effective widths of 25 nm upon lateral-gate biasing. Device operation is demonstrated for protein-specific binding, and it is found that sensitive detection signals are recorded once the channel width is comparable with the dimensions of the protein. The device performance is discussed and analyzed with the help of three-dimensional electrostatic simulations. A team of researchers from Israel, led by Yossi Rosenwaks at Tel Aviv University, has devised a facile route towards nanowire-based, label-free biosensors. These sensors have recently garnered interest for applications in biological species such as proteins, DNA or viruses: the presence of the target molecule is detected and converted into an electrical signal. But bottom-up strategies to prepare the nanowires are difficult to scale-up, while top-down approaches involve a relatively complex process. In contrast, the biosensor devised by Rosenwaks and co-workers is organized around a nanowire-like conducting channel that is formed electrostatically after device fabrication. The rectangular device comprises four gates at each extremity and these form depletion regions between which the channel is defined. Biomolecules are then detected with a sensitivity that depends on the size, shape and location of the channel — the presence of proteins was successfully determined at femtomolar concentrations. This combined approach brings together good performance with standard integrated circuit processing and holds great promise for real-time diagnostic applications. Biological sensing with silicon nanowires has drawn much attention due to the enhanced sensitivity of these devices. However, both bottom-up and top-down fabrication techniques are thus far resistant to commercialization, mainly due to the incompatibility of the bottom-up methodology with mass production and the non-standard, top-down process complexity. We report on a specific, label-free, and real-time detection of femtomolar protein concentrations with a novel type of nanowire-based biosensor. The biosensor is based on an electrostatically formed nanowire that requires standard integrated circuit processes with relaxed fabrication requirements.

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Specific and label-free femtomolar biomarker detection with an electrostatically formed nanowire biosensor

An overview is given on the low-frequency (LF) noise of silicon-on-insulator (SOI) devices and technologies. In the first two parts, noise mechanisms specific for SOI are discussed, namely, the front–back-gate coupling in fully-depleted MOSFETs and the Lorentzian noise overshoot in floating-body operating transistors. In the next part, the impact of the technology (SOI substrate, gate stack processing, isolation module, …) on the LF noise is described. From this, it is derived that scaling below the 0.25 μm CMOS node did not result in the anticipated reduction of the 1/f noise with tfox or t fox 2 . This is related to the increasing amount of nitrogen incorporated in the thin SiON front gate oxides with thickness tfox. In the case of high-κ dielectrics it is frequently observed that these have a higher trap density compared to SiO2. On the other hand, today’s multigate SOI transistors seem to give rise to similar gate oxide trap densities and hence, 1/f noise, than their single-gate counterparts. In the last part, operational and circuit aspects will be discussed, which might have a beneficial impact on the LF noise performance.

Low-frequency noise in silicon-on-insulator devices and technologies

The four-gate silicon-on-insulator transistor (G/sup 4/-FET) combines MOS and JFET actions in a single transistor to control the drain current. The various operation modes of the G/sup 4/-FET are analyzed, based on the measured current-voltage, transconductance and threshold characteristics. The main parameters (threshold voltage, swing, mobility) are extracted and shown to be optimized for particular combinations of gate biasing. Numerical simulations are used to clarify the role of volume or interface conduction mechanisms. Besides excellent performance (such as subthreshold swing and transconductance) and unchallenged flexibility, the new device has the unique feature to allow independent switching by its four separate gates, which inspires many innovative applications.

Investigation of the four-gate action in G/sup 4/-FETs

The two-dimensional (2-D) channel potential and threshold voltage of the silicon-on-insulator (SOI) four-gate transistor (G4-FET) are modeled. The 2-D analytical body potential is derived by assuming a parabolic potential variation between the lateral junction-gates and by solving Poisson's equation. The model is used to obtain the surface threshold voltage of the G4-FET as a function of the lateral gate bias and for all possible charge conditions at the back interface. The body-potential model is extendable to fully depleted SOI MOSFETs and can serve to depict the charge-sharing and drain-induced barrier-lowering effects in short-channel devices

Analytical modeling of the two-dimensional potential distribution and threshold voltage of the SOI four-gate transistor

In the silicon-on-insulator four-gate transistors (G4-FETs), the conducting channel can be surrounded by depletion regions induced by independent vertical metal-oxide-semiconductor gates and lateral JFET gates. This unique conduction mechanism named depletion-all-around (DAA) enables majority carriers to flow in the volume of the silicon film far from the silicon/oxide interfaces. Especially when the interfaces are driven to inversion, the control of the lateral JFET gates on the conduction is maximized, while the sensitivity of the volume channel to the oxide and interface defects is minimized. This leads to excellent analog performance, low noise, and reduced sensitivity to ionizing radiation. The G4-FET properties in DAA mode are presented from multiple perspectives: experimental results, 3-D device simulations, and analytical modeling

Depletion-All-Around Operation of the SOI Four-Gate Transistor

The influence of the fin width on substrate-to-gate coupling in long-channel silicon-on-insulator triple-gate transistors is investigated. A complementary analysis, taking into account both the "front coupling" (variation of the front-channel threshold voltage VT1, as a function of the substrate bias VG2) and "back coupling" (variation of the back-channel threshold voltage VT2) as a function of the front-gate bias VG1) characteristics has been carried out. It is shown that the back coupling, as opposed to the front coupling, is highly sensitive to the fin width in narrow-channel devices and can even be used in fin width extraction. Simple analytical 2-D models for the body potential, VT1, and VT2 have been developed to clarify the experimental data, showing in particular the gradual control of the back interface potential by the lateral gates in narrow fins. The model stands as a 2-D generalization of the Lim and Fossum's well-known 1-D interface coupling model

A Two-Dimensional Model for Interface Coupling in Triple-Gate Transistors

The G4-FET, a four-gate transistor compatible with standard silicon-on-insulator (SOI) CMOS technology, provides unique opportunities as a logic device. Combining both JFET- and MOSFET-like actions within one transistor body, the G4-FET offers two side (lateral) junction-based gates, a top MOS gate, and a MOS back gate that is activated by SOI substrate biasing. The G4-FET's conduction characteristics are controlled by the combined interaction of these four gates. In this paper, the G4-FET is demonstrated as a logic device, resulting in a universal and programmable logic gate that can lead to the design of more efficient logic circuits. As an example, we present a new full adder design based on the G4-FET that is significantly more efficient than conventional designs.

K. Akarvardar

Papers

Investigation of the four-gate action in G/sup 4/-FETs

Analytical modeling of the two-dimensional potential distribution and threshold voltage of the SOI four-gate transistor

Depletion-All-Around Operation of the SOI Four-Gate Transistor

A Two-Dimensional Model for Interface Coupling in Triple-Gate Transistors

The G4-FET: a universal and programmable logic gate