An analytic potential-based model for the undoped surrounding-gate MOSFETs is derived in the paper. The model is obtained from rigorously solving Poisson equation together with the drain-current formulation equivalent to Pao-Sah's double integral that is previously proposed for long-channel bulk MOSFETs. The model consists of an analytic drain-current equation that accounts for both drift and diffusion current components in terms of the potential at the oxide silicon interface and the silicon center of device body evaluated at the source and drain terminals. The model gives a fully self-consistent physical description for the channel potential, charge, and current that is valid for the subthreshold, linear, and saturation regions. The validity of the proposed model has been verified by extensive comparison with the exact numerical integrations and 2-D numerical simulation, which demonstrates model accuracy and prediction capability.

An Analytic Potential-Based Model for Undoped Nanoscale Surrounding-Gate MOSFETs

A continuous and analytic channel potential solution for undoped (lightly doped) surrounding-gate (SRG) MOSFETs is presented in this article. It is based on the exact solution of Poisson’s equation, allowing the surface potential to be adequately described from the sub-threshold to strong inversion region. It is demonstrated that the analytic channel potential characteristics agree with the Newton–Raphson iterative solutions for all ranges of gate and quasi-Fermi-potential.

Analytic channel potential solution to the undoped surrounding-gate MOSFETs

A compact model is proposed for accurately incorporating effects of STI (shallow trench isolation) stress into post-layout simulation by making layout-dependent corrections to SPICE model parameters. The model takes in-plane (longitudinal and transverse) and normal components of the layout-dependent stress into account, and model formulas are devised from physical considerations. Not only can the model handle the shape of the active-area of any MOSFET conforming to design rules, but also considers distances to neighboring active-areas. Extraction of geometrical parameters from the layout can be performed by standard LVS (layout versus schematic) tools, and the corrections can subsequently be back-annotated into the netlist. The paper spells out the complete formulation by presenting expressions for the mobility and the threshold voltage explicitly by way of example. The model is amply validated by comparisons with experimental data from 90 nm- and 65 nm-CMOS technologies having the channel orientations of, respectively, (110) and (100), both on a (100) surface. The worst-case standard errors turn out to be as small as 1.7% for the saturation current and 8 mV for the threshold voltage, as opposed to ∼20% and ∼50 mV without the model. Since device characteristics variations due to STI stress constitute a significant part of what have conventionally been treated as random variations, use of the proposed model could enable one to greatly narrow the guardbands required to guarantee a desired yield, thereby facilitating design closure.

Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress

While floating-gate MOS transistor in mixed-signal applications have been studied in the literature, little has been reported on modeling them with gate leakage current (GLC). This paper presents a simulation model for floating-gate MOS transistor in nanometer-scale technologies. The proposed model accounts for direct tunnelling GLC in sub 3 nm gate oxide thickness. The model can be used for both transient and DC simulations with any industry standard simulators. HSPICE simulations and measurements of an experimental chip using TSMC 90 nm technology were presented.

Modelling of direct tunneling gate leakage current of floating-gate CMOS transistor in sub 100 nm technologies

An analytic potential-based model for the undoped surrounding-gate MOSFETs is derived in the paper. The model is obtained from solving Poisson equation rigorously together with the drain current formulation equivalent to Pao-Sahpsilas double integral previously proposed for long-charnel bulk MOSFETs. The model gives a fully self-consistent physical description for the channel potential, charge and current that is valid for the sub threshold, linear and saturation regions. The validity of the proposed model has been verified by extensive comparison with the exact numerical integrations and 3-D numerical simulation , demonstrating the modelpsilas accuracy and prediction capability.

An analytic potential-based model for undoped nanoscale surrounding-gate MOSFETs

New technologies and alternate transistor structures are being developed to extend the CMOS scaling. Device models need to be developed and improved in parallel with the technology advancements to enable an efficient and quick adoption of the new technologies. Some of the recent advances in BSIM4 and BSIM Multi-gate models towards meeting this goal are presented in this paper. Improvements to the BSIM4 model include holistic stress-induced mobility enhancement model and a high-k dynamic behavior model. Preliminary results of the modeling of multi-gate architectures are also presented.

https://briefs.techconnect.org/wp-content/volumes/Nanotech2006v3/pdf/1074.pdf

S. Chen

Papers

BSIM4 and BSIM Multi-Gate Progress