C
Chung Hsun Lin
Researcher at University of California, Berkeley
Publications - 13
Citations - 271
Chung Hsun Lin is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & BSIM. The author has an hindex of 8, co-authored 13 publications receiving 260 citations. Previous affiliations of Chung Hsun Lin include IBM & University of California.
Papers
More filters
Proceedings ArticleDOI
A 0.063 µm 2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
V. Basker,Theodorus E. Standaert,H. Kawasaki,C.-C. Yeh,Kingsuk Maitra,Tenko Yamashita,J. Faltermeier,H. Adhikari,Hemanth Jagannathan,Junli Wang,Hiroshi Sunamura,S. Kanakasabapathy,Stefan Schmitz,Jason E. Cummings,Atsuro Inada,Chung Hsun Lin,Pranita Kulkarni,Yu Zhu,J. Kuss,T. Yamamoto,Amit Kumar,Jeremy A. Wahl,Atsushi Yagishita,Lisa F. Edge,R. H. Kim,Erin Mclellan,S. Holmes,R. C. Johnson,T. Levin,James J. Demarest,Masami Hane,Mariko Takayanagi,Matthew E. Colburn,Vamsi Paruchuri,R. J. Miller,Huiming Bu,Bruce B. Doris,D. McHerron,Effendi Leobandung,James A. O’Neill +39 more
TL;DR: In this paper, the smallest FinFET SRAM cell size of 0.063 µm2 has been achieved using optical lithography using a double-expose, double-etch (DE2) sidewall image transfer (SIT) process.
Book ChapterDOI
BSIM-CMG: A compact model for multi-gate transistors
TL;DR: In this article, the authors proposed the use of multiple gates to reduce the coupling between source and drain in the sub-threshold region and enable the multigate transistor to be scaled beyond bulk planar CMOS for a given dielectric thickness.
Journal ArticleDOI
A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates
TL;DR: In this paper, a computationally efficient surface-potential-based compact model for fully-depleted SOI MOSFETs with independently-controlled front and back-gates is presented.
Book ChapterDOI
Multi-Gate MOSFET Compact Model BSIM-MG
TL;DR: BSIM-MG: a versatile compact model for multi-gate MOSFETs, derived and agree well with TCAD simulations without using fitting parameters, reflecting the predictivity and scalability of the model.
Proceedings ArticleDOI
Circuit performance of double-gate SOI CMOS
TL;DR: In this paper, the performance of double-gate MOSFETs in the circuit design perspective is examined via simulation using device structures based on the ITRS specification, and the performance result showed superiority of SDG device over ADG device in speed and energy efficiency.