FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.

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FinFETs and Other Multi-Gate Transistors

A predictive MOSFET model is critical for early circuit design research. In this work, a new generation of Predictive Technology Model (PTM) is developed, covering emerging physical effects and alternative structures, such as the double-gate device (i.e., FinFET). Based on physical models and early stage silicon data, PTM of bulk and double-gate devices are successfully generated from 130nm to 32nm technology nodes, with effective channel length down to 13nm. By tuning only ten primary parameters, PTM can be easily customized to cover a wide range of process uncertainties. The accuracy of PTM predictions is comprehensively verified with published silicon data: the error of the current is below 10p for both NMOS and PMOS. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime. PTM is available online at http://www.eas.asu.edu/~ptm.

Predictive technology model for nano-CMOS design exploration

(IEEE Transactions on Electron Devices,36(12):2816-2820)Field-Drifting Resonant Tunneling Through a-Si:H/a-Sil-xCx:H Quantum Wells at Different Locations of the i-Layer of a p-i-n Structure

Predictive MOSFET models are critical for early stage design-technology co-optimization and circuit design research In this work, Predictive Technology Model files for sub-20nm multi-gate transistors have been developed (PTM-MG) Based on MOSFET scaling theory, the 2011 ITRS roadmap and early stage silicon data from published results, PTM for FinFET devices are generated for 5 technology nodes corresponding to the years 2012-2020 on the ITRS roadmap

Exploring sub-20nm FinFET design with predictive technology models

Well-designed circuits are one key Binsulating( layer between the increasingly unruly behavior of scaled complementary metal-oxide-semiconductor devices and the systems we seek to construct from them. As we move forward into the nanoscale regime, circuit design is burdened to Bhide( more of the problems intrinsic to deeply scaled devices. How this is being accomplished is the subject of this paper. We discuss new techniques for logic circuits and interconnect, for memory, and for clock and power distribution. We survey work to build accurate simulation models for nanoscale devices. We discuss the unique problems posed by nanoscale lithography and the role of geometrically regular circuits as one promising solution. Finally, we look at recent computer-aided design efforts in modeling, analysis, and optimization for nanoscale designs with ever increasing amounts of statistical variation.

Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS : Small transistors necessitate big changes, in the way digital circuits are modeled and optimized for manufacturability, and new strategies for logic, memory, clocking and power distribution

The need for meeting the expectations of continuing the enhancement of CMOS performance and density has inspired the introduction of new materials into the classical single-gate bulk MOSFET and the development of nonclassical multigate transistors at an accelerated rate. There is a strong need to understand and model the associated new physics and electrical behavior to ensure widespread very-large-scale-integration circuit applications of new technologies. This paper presents some of the efforts toward the modeling of new technologies for bulk MOSFETs and multigate transistors. A holistic model for mobility enhancement through process-induced stress and a dynamic behavior model for high-k transistors have been developed to capture some of the new effects and new materials in the bulk MOSFET. A new analytical model is also presented for the fundamentally new device structure-FinFET

Modeling Advanced FET Technology in a Compact Model

The scaling of conventional planar CMOS is expected to become increasingly difficult due to increasing gate leakage and subthreshold leakage.[1-2] Multi-gate FETs such as FinFETs have emerged as the most promising candidates to extend the CMOS scaling into the sub-25nm regime.[3-4] The strong electrostatic control over the channel originating from the use of multiple gates reduces the coupling between source and drain in the subthreshold region and it enables the Multigate transistor to be scaled beyond bulk planar CMOS for a given dielectric thickness. Numerous efforts are underway to enable large scale manufacturing of multi-gate FETs. At the same time, circuit designers are beginning to design and evaluate multi-gate FET circuits.

BSIM-CMG: A compact model for multi-gate transistors

A novel surface-potential based multi-gate FET (MG-FET) compact model has been developed for mixed-signal design applications. For the first time, a MG-FET model captures the effect of finite body doping on the electrical behavior of MG-FETs. A unique field penetration length model has been developed to model the short channel effects in MG-FETs. A multitude of physical effects such as poly-depletion effect and quantum-mechanical effect (QME) have been incorporated. The expressions for terminal currents and charges are co-continuous making the model suitable for mixed-signal design. The model has been verified extensively with TCAD and experimental data.

BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design

This paper outlines the charge-based core and the model architecture of the BSIM5, an advanced charge-based MOSFET model for nanoscale VLSI circuit simulation. Compared with the previous charge-based models with an assumption of the linearization of the bulk and inversion charges with respect to the surface potential at a fixed gate bias, the BSIM5 model is directly derived from the solution of the Poisson equation coupled to the current density equation. The comparisons of the inversion charge and the channel current between the BSIM5 and the Pao–Sah model indicate that the BSIM5 model maintains the inherent device physics and high accuracy of the Pao–Sah model. BSIM5 model is further extended to include the short-channel effects, narrow-width-effects, and the wide comparison with the experiment data demonstrates its validity to simulate the nanoscale circuits. Moreover, the symmetry and RF function of BSIM5 have also been demonstrated in the Gummel tests and high-order distortion analysis.

BSIM5: An advanced charge-based MOSFET model for nanoscale VLSI circuit simulation

A compact model for multi-gate MOSFETs with two independently-biased gates is presented. The core model is verified against TCAD simulations without the use of any fitting parameters. Real device effects such as short channel effects and body doping effects are captured. The use of the model is demonstrated through two simulation examples: (1) Back-gate dynamic feedback of FinFET SRAM cells and (2) Tuning of device variations through back gate biasing.

Mohan Dunga

Papers

Modeling Advanced FET Technology in a Compact Model

BSIM-CMG: A compact model for multi-gate transistors

BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design

BSIM5: An advanced charge-based MOSFET model for nanoscale VLSI circuit simulation

A Multi-Gate MOSFET Compact Model Featuring Independent-Gate Operation