http://ieeexplore.ieee.org/iel5/5610941/5624686/05624745.pdf

Power electronics

Review of multilevel voltage source inverter topologies and control schemes

A photovoltaic (PV) array has non-linear I–V (current–voltage) characteristics and its output power varies with solar insolation level and ambient temperature. There exists only one point, called maximum power point (MPP), on the P–V (power–voltage) curve, where power is maximum and this point varies with the changing atmospheric conditions. Moreover, energy conversion efficiency of PV module is very low and mismatch between source and load characteristics causes significant power losses. Consequently, maximization of power output with greater efficiency is extremely important. Maximum power point tracking (MPPT) is a technique employed to extract maximum power available from the PV module. It traces the PV operating voltage corresponding to the MPP and locks the operating point at MPP and extract maximum power from the array. Till date, many algorithms for MPPT have been reported, each with its own features. In this paper, a comprehensive presentation of working principle of these techniques is made and they are compared against each other in terms of some critical parameters like: number of variables used, complexity, accuracy, speed, hardware implementation, cost, tracking efficiency and so on. This study is aimed at providing a compendium on MPPT techniques for an appropriate selection, based on application requirements and system constraints.

Maximum power point tracking control techniques: State-of-the-art in photovoltaic applications

Multilevel inverters (MLIs) are being used in wide range of power electronic applications. These converters have attracted a lot of attention during recent years and exist in different topologies with similar basic concepts. This paper presents five main submodules (SMs) to be used as the basic structures of MLIs. The paper reviews the common MLI topologies from the structural point of view. The topologies are divided into the different SMs to show conventional MLI configurations and future topologies that can be created from the main SMs. A comparative study between different topologies is performed in detail. The MLIs are categorized and investigated with from different perspectives such as the number of components, the ability to create inherent negative voltage, working in regeneration mode and using single dc source.

A General Review of Multilevel Inverters Based on Main Submodules: Structural Point of View

A new MPPT controller based on the Ant colony optimization algorithm for Photovoltaic systems under partial shading conditions

FPGA based practical implementation of NPC-MLI with SVPWM for an autonomous operation PV system with capacitor balancing

A new series parallel switched multilevel dc-link inverter topology

This paper deals with a novel natural sampled pulse width modulation (PWM) switching strategy for voltage source inverter through carrier modification. The proposed inverted sine carrier PWM (ISCPWM) method, which uses the conventional sinusoidal reference signal and an inverted sine carrier, has a better spectral quality and a higher fundamental component compared to the conventional sinusoidal PWM (SPWM) without any pulse dropping. The ISCPWM strategy enhances the fundamental output voltage particularly at lower modulation index ranges while keeping the total harmonic distortion (THD) lower without involving changes in device switching losses. The presented mathematical preliminaries for both SPWM and ISCPWM give a conceptual understanding and a comparison of the strategies. The detailed comparison of the harmonic content and fundamental component of the ISCPWM output for different values of modulation index with the results obtained for the SPWM is also presented. Finally, the proposed modulator has been implemented in field programmable gate array (FPGA- Xilinx Spartan 3) and tested with the proto-type inverter.

/pdf/inverted-sine-carrier-for-fundamental-fortification-in-pwm-1a75sp3n74.pdf

Inverted Sine Carrier for Fundamental Fortification in PWM Inverters and FPGA Based Implementations

The purpose of this study is to provide a broad idea about current control scheme and equilibrating voltages in DC-link capacitors of the neutral-point clamped multilevel inverter (NPC-MLI), using an innovative hexagonal space vector hysteresis current control (SVHCC) scheme. The main ideology is to force the literal current vector to reach the reference current vector through an appropriate voltage vector selection sequence. This proposed scheme defines two hexagonal hysteresis bands encompassing the error vector, as a first step. With respect to the error vector location, the selection of the adjacent vector is acted to minimise the error vector. In addition to the error vector selection, the capacitor voltage is also equilibrated by controlling the degree of freedom available in selecting the switching vectors. The SVHCC scheme is intelligent in performing modulation depth dependent selection of switching vectors between the groups namely closest three vector and preferred three vector (PTV). This scheme balances the DC-link capacitors’ voltages within a tolerance limit for any value of modulation index. The proposed scheme is asserted through MATLAB/Simulink software. The superiority of the proposed technique is validated through the 2 kW NPC-MLI supported with SPARTAN III 3AN –XC3S400 field programmable gate array.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet-pel.2015.0184

Vector selection approach-based hexagonal hysteresis space vector current controller for a three phase diode clamped MLI with capacitor voltage balancing

This study proposes a novel topology for reducing commutation torque ripple in a brushless DC motor (BLDCM) drive system using a three-level neutral-point-clamped (NPC) inverter combined with single-ended primary-inductor converter (SEPIC) converters. In the BLDCM, current ripples arise because of the influence of stator winding inductance, which generates torque ripples. The torque ripple that is generated in the commutation period prevents the use of BLDCM in high-precision servo drive systems. In this study, two-stage converters are proposed to reduce the torque ripple. The first stage consists of two SEPIC converters to obtain the desired commutation voltage according to motor speed. A dc-link voltage selection circuit is combined with the SEPIC converters to apply the optimised voltage during the commutation interval. To reduce the torque ripple further, a three-level NPC inverter is used to apply a half dc-link voltage across the motor winding and this effectively reduces the torque ripple. Experimental results show that the proposed topology is able to reduce commutation torque ripple significantly under both low-speed and high-speed operation.

https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-pel.2013.0471

S. Jeevananthan

Papers

FPGA based practical implementation of NPC-MLI with SVPWM for an autonomous operation PV system with capacitor balancing

A new series parallel switched multilevel dc-link inverter topology

Inverted Sine Carrier for Fundamental Fortification in PWM Inverters and FPGA Based Implementations

Vector selection approach-based hexagonal hysteresis space vector current controller for a three phase diode clamped MLI with capacitor voltage balancing

Approach for torque ripple reduction for brushless DC motor based on three-level neutral-point-clamped inverter with DC–DC converter