In this paper we present a novel integrated approach to on-line FPGA testing, diagnosis, and fault-tolerance, to be used in high-reliability and high-availability hardware. The test process takes place in self-testing areas (STARs) of the FPGA, without disturbing the normal system operation. The entire chip is eventually tested by having (STARs) gradually rove across the FPGA. Our approach guarantees complete testing of programmable logic blocks and interconnect, and provides maximum diagnostic resolution. A new fault-tolerant (FT) technique allows using partially defective FPGA resources for normal operation, providing longer mission life-span in the presence of faults. We also introduce the basic concepts of a new dynamic FT method, spare resources needed to bypass a fault are always in the neighborhood of the located fault, thus simplifying fault-bypassing.

Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications

As feature sizes shrink closer to single digit nanometer dimensions, defect tolerance will become increasingly important. This is true whether the chips are manufactured using top-down methods, such as photolithography, or bottom-up assembly processes such as Chemically Assembled Electronic Nanotechnology (CAEN). In this chapter, we examine the consequences of this increased rate of defects, and describe a defect tolerance methodology centered around reconfigurable devices, a scalable testing method, and dynamic place-and-route. We summarize some of our own results in this area as well as those of others, and enumerate some future research directions required to make nanometer-scale computing a reality.

/pdf/defect-tolerance-at-the-end-of-the-roadmap-149j3m3yps.pdf

Defect tolerance at the end of the roadmap

We present a built-in self-test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also identify and solve the problem of testing configuration multiplexers that was either ignored or incorrectly solved in most previous work. We introduce the first diagnosis method for multiple faulty PLBs; for any faulty PLB, we also identify its internal faulty modules or modes of operation. Our accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs. Our BIST architecture is easily scalable.

BIST-based test and diagnosis of FPGA logic blocks : Reconfigurable and Adaptive VLSI Systems

/pdf/bist-based-test-and-diagnosis-of-fpga-logic-blocks-13aspjqt6j.pdf

BIST-based test and diagnosis of FPGA logic blocks

Lithium-ion battery (LIB) degradation originates from complex mechanisms, usually interacting simultaneously in various degrees of intensity. Due to its complexity, to date, identifying battery aging mechanisms remains challenging. Recent improvements in battery degradation identification have been developed, including validated, in situ incremental capacity (IC) and peak area (PA) analysis. Due to their in situ and non-destructive nature, IC and PA implementation is feasible in on-board battery management systems (BMSs). Despite their advantages, the understanding and applicability of IC and PA techniques is not straightforward, as it requires both electrochemical and material science backgrounds. However, BMS design teams are mainly integrated by electrical engineers and may not include battery scientists. Aiming to bridge gaps in knowledge between electrical engineering and battery science toward battery degradation identification, here we present a systematic approach consisting in a set of lookup tables generated from IC and PA techniques. The lookup tables provide a simple, yet reliable, tool for the evaluation of LIB degradation modes. Various real-life examples of cell degradation are also presented to illustrate and validate the use of the proposed approach. This study exemplifies the use of lookup tables providing a simple, fast, and accurate automated estimation of LIB degradation modes to be implemented in BMSs.

/pdf/lithium-ion-battery-degradation-indicators-via-incremental-4fxnhqsi3s.pdf

Lithium-Ion Battery Degradation Indicators Via Incremental Capacity Analysis

Focusing on configurable logic blocks in a lookup table FPGA, the authors present universal fault diagnosis procedures that can locate a fault to just one CLB. The complexity of the proposed procedure for FPGAs using block-sliced loading is independent of FPGA array size.

S. Miyazaki

Papers

Universal fault diagnosis for lookup table FPGAs