We are developing n+-in-p, p-bulk and n-readout, microstrip sensors, fabricated by Hamamatsu Photonics, as a non-inverting radiation hard silicon detector for the ATLAS tracker upgrade at the super-LHC (sLHC) proposed facility. The bulk radiation damage after neutron and proton irradiations is characterized with the leakage current, charge collection and full depletion voltage. The detectors should provide acceptable signal, signal-to-noise ratio exceeding 15, after the integrated luminosity of 6000 fb−1, which is twice the sLHC integrated luminosity goal.

/pdf/testing-of-bulk-radiation-damage-of-n-in-p-silicon-sensors-15vcakysbt.pdf

Testing of bulk radiation damage of n-in-p silicon sensors for very high radiation environments

This paper describes the baseline integration structures for the silicon strip sensors to be used in the ATLAS detector for the Phase-II upgrade of the Large Hadron Collider (LHC) machine, the so-called High Luminosity LHC (HL-LHC). Highly modular structures have been developed for the integration of the silicon strips sensors, readout electronics, cooling, and support structures, called ‘staves’ for the barrel region and ‘petals’ for the end-caps of the ATLAS strips tracker. This work describes the status of the current prototypes, the building procedure, designed for mass production even at a prototyping stage, and their electrical performances.

/pdf/silicon-strip-staves-and-petals-for-the-atlas-upgrade-yli1zdjmc2.pdf

Silicon strip staves and petals for the ATLAS Upgrade tracker of the HL-LHC

The LHCb experiment at the LHC plans to massively increase its data taking capabilities by running at a higher luminosity with a fully upgraded detector around 2016. This scheme is independent of (but compatible with) the plans for the SLHC upgrades. The silicon detector will be upgraded to provide a 40 MHz readout and to be able to cope with the increased radiation environment. This paper describes the options currently under consideration. A highlight of the R&D so far undertaken is a beam test during summer 2009 using the Timepix chip to track charged particles. Preliminary results are presented, including a measurement of the resolution achieved by the 55μm pitch pixel array of better than 9.5μm for perpendicular tracks and 55μm for angled tracks. © 2010 Elsevier B.V.

/pdf/the-lhcb-velo-upgrade-2pj3wx8k2m.pdf

The LHCb VELO Upgrade

We present the design and performance of the ABCN-25 readout chip implemented in 025 μm CMOS technology The front-end design has been optimized for the short, 25 cm, silicon strips foreseen in the upgrade of the ATLAS Inner Detector The core of the readout architecture includes binary front-end, two levels of data buffering, data compression and data serializing circuitry, and is similar to the architecture of the ABCD3T chip used in the present ATLAS SCT detector In order to ensure required radiation hardness the hardening by layout technique has been used and SEU detection and correction circuitry have been added The design includes on-chip power management circuitry comprising two types of shunt regulators and a serial regulator This circuitry makes the ABCN-25 chip compatible with recent developments in the area of power distribution systems for the inner trackers in the SuperLHC environment and in particular with serial powering of the detector modules The chip has been fabricated in 025 μm CMOS technology and full functionality has been obtained The critical design aspects and performance of the analog and digital circuits will be presented and discussed

Design and performance of the ABCN-25 readout chip for ATLAS Inner Detector Upgrade

The ATLAS detector is a general purpose experiment designed to fully exploit the discovery potential of the Large Hadron Collider (LHC) at a nominal luminosity of 10 34  cm −2  s −1 . It is expected that after several years of successful data-taking, the LHC physics program will be extended by increasing the peak luminosity by one order of magnitude. For ATLAS, an upgrade scenario will imply the complete replacement of the Inner Detector (ID), since the current tracker will not provide the required performance due to cumulated radiation damage and a dramatic increase in the detector occupancy. In this paper, a proposal of a double-sided silicon micro-strip module for the short-strip region of the future ATLAS ID is presented. The expected thermal performance based upon detailed FEA simulations is discussed. First electrical results from a prototype version of the next generation readout front-end chips are also shown.

A silicon strip module for the ATLAS inner detector upgrade in the super LHC collider

The ATLAS experiment is preparing for the planned luminosity upgrade of the LHC (the super-luminous LHC or sLHC) with a programme of development for tracking able to withstand an order of greater magnitude radiation fluence and much greater hit occupancy rates than the current detector. This has led to the concept of an all-silicon tracker with an enhanced performance pixel-based inner region and short-strips for much of the higher radii. Both sub-systems employ many common technologies, including the proposed “stave” concept for integrated cooling and support. For the short-strip region, use of this integrated stave concept requires single-sided modules mounted on either side of a thin central lightweight support. Each sensor is divided into four rows of 23.82 mm length strips; within each row, there are 1280 strips of 74.5μm pitch. Well over a hundred prototype sensors are being delivered by Hamamatsu Photonics (HPK) to Japan, Europe and the US. We present results of the first 20 chip ABCN25 ASIC hybrids for these sensors, results of the first prototype 5120 strip module built with 40 ABCN25 read-out ASICs, and the status of the hybrids and modules being developed for the ATLAS tracker upgrade stave programme.

Progress with the single-sided module prototypes for the ATLAS tracker upgrade stave

We present the test results of the ABCN-25 front end chip implemented in CMOS 0.25 μm technology and optimised for the short, 2.5 cm, silicon strips intended to be used in the upgrade of the ATLAS Inner Detector. We have obtained the full functionality of the readout part, the expected performance of the analogue front-end and the operation of the power control circuits. The performance is evaluated in view of the minimization of the power consumption, as the upgrade detector may contain up to 70 million of channels. System tests with different power distribution schemes proposed for the future tracker detectors are possible with this chip. The ABCN-25 ASIC is now serving as the prototype readout chip in the developments of the modules and staves for the upgrade of the ATLAS Inner Detector.

/pdf/performance-of-the-abcn-25-readout-chip-for-the-atlas-inner-51apd29t4w.pdf

S. Pernecker

Papers

Progress with the single-sided module prototypes for the ATLAS tracker upgrade stave

Performance of the ABCN-25 readout chip for the ATLAS Inner Detector Upgrade