Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

Scaling the Si MOSFET is reconsidered. Requirements on subthreshold leakage control force conventional scaling to use high doping as the device dimension penetrates into the deep-submicrometer regime, leading to an undesirably large junction capacitance and degraded mobility. By studying the scaling of fully depleted SOI devices, the important concept of controlling horizontal leakage through vertical structures is highlighted. Several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design. The concept of vertical doping engineering can also be realized in bulk Si to obtain good subthreshold characteristics without large junction capacitance or heavy channel doping. >

Scaling the Si MOSFET: from bulk to SOI to bulk

Experiments on ultra‐small metal‐oxide‐semiconductor field effect transistors (MOSFETs) less than 100 nm have been widely reported recently. The frequency of carrier scattering events in these ultra‐small devices is diminished, so that further suppression of carrier scattering may bring these devices close to the regime of ballistic transport. Carrier scattering is suppressed by constructing their channel regions with intrinsic Si and also by low temperature operation. This article proposes the ballistic transport of carriers in MOSFETs, and presents the current‐voltage characteristics of the ballistic n‐channel MOSFET. The current is expressed with the elementary parameters without depending on the carrier mobility. It is independent of the channel length and is proportional to the channel width. The current value saturates as the drain voltage is increased and the triode and the pentode operation are specified as in the conventional MOSFET. Similar current‐voltage characteristics in the ballistic transport regime are also investigated for the p‐channel MOSFET, the dual gate ultra‐thin silicon on insulator MOSFET, and the high electron mobility transistor device. The obtained current gives the maximum current limitation of each field effect transistor geometry. The current control mechanism of ballistic MOSFETs is discussed. The current value is governed by the product of the carrier density near the source edge in the channel, and the velocity with which carriers are injected from the source into the channel.Influence of optical phonon emission to the transport is discussed. It is suggested that if the device is operated with relatively low carrier density at low temperatures, and if the scattering processes other than the optical phonon emission are suppressed so as to attain the ballistic transport, the optical phonon emission is also suppressed and ballistic transport is sustained. A convenient figure of merit to show the ballisticity of carrier transport in an experimental MOSFET is proposed. Its value is estimated for some examples of the recent ultra‐small MOSFET experiment. The proposed current voltage characteristics are evaluated for a dual gate silicon on insulator MOSFET geometry. The result is compared with the recently reported elaborate Monte Carlo simulation with satisfactory agreement.

/pdf/ballistic-metal-oxide-semiconductor-field-effect-transistor-1mt2btaxea.pdf

Ballistic metal-oxide-semiconductor field effect transistor

A simple one-flux scattering theory of the silicon MOSFET is introduced. Current-voltage (I-V) characteristics are expressed in terms of scattering parameters rather than a mobility. For long-channel transistors, the results reduce to conventional drift-diffusion theory, but they also apply to devices in which the channel length is comparable to or even shorter than the mean-free-path. The results indicate that for very short channels the transconductance is limited by carrier injection from the source. The theory also indicates that evaluation of the drain current in short-channel MOSFETs is a near-equilibrium transport problem, even though the channel electric field is large in magnitude and varies rapidly in space.

Elementary scattering theory of the Si MOSFET

http://inis.jinr.ru/sl/P_Physics/PT_Thermodynamics,%20statistical%20physics/Mirlin%20Statistics.pdf

Statistics of energy levels and eigenfunctions in disordered systems

Transport properties are investigated in self-aligned NMOS devices with gate lengths down to 0.07 mu m. Velocity overshoot was observed in the form of the highest transconductances measured to date in Si FETs, as well as in the trend of the transconductance with gate length. The measured transconductance reached 910 mu S/ mu m at liquid-nitrogen temperature and 590 mu S/ mu m at room temperature. Velocity overshoot, by making such transconductances possible, should extend the value of miniaturization to dimensions that are smaller than what was commonly assumed to be worthwhile to pursue. >

High transconductance and velocity overshoot in NMOS devices at the 0.1- mu m gate-length level

The exposure distribution function in electron beam lithography, which is needed to perform proximity correction, is usually simulated by Monte Carlo techniques, assuming a Gaussian distribution of the primary beam. The resulting backscattered part of the exposure distribution is usually also fitted to a Gaussian term. In this paper we demonstrate a technique, using a very high contrast resist, whereby the normalized point exposure distribution can be measured experimentally, both on solid substrates which cause backscattering, and on thin substrates where backscattering is negligible. The data sets so obtained can be applied directly to proximity correction and represent the practical conditions met in pattern writing. Results are presented of the distributions obtained on silicon, gallium arsenide, and thin silicon nitride substrates at different beam energies. Significant deviations from the commonly assumed double Gaussian distributions are apparent. On GaAs substrates the backscatter distribution cannot adequately be described by a Gaussian function. Even on silicon a significant amount of exposure is found in the transition region between the two Gaussian terms. This deviation, which can be due to non‐Gaussian tails in the primary beam and to forward scattering in the resist, must be taken into account for accurate proximity correction in most submicron lithography, and certainly on the sub‐100 nm scale.

Point exposure distribution measurements for proximity correction in electron beam lithography on a sub‐100 nm scale

The first device performance results are presented from experiments designed to assess FET technology feasibility in the 0.1-µm gate-length regime. Low-temperature device design considerations for these dimensions lead to a 0.15-V threshold and 0.6-V power supply, with a forward-biased substrate. Self-aligned and almost fully scaled devices and simple circuits were fabricated by direct-write electron-beam lithography at all levels, with gate lengths down to 0.07 µm. Measured device characteristics yielded over 750-mS/mm transconductance, which is the highest value obtained to date in Si FET's.

Design and experimental technology for 0.1-&#181;m gate-length low-temperature operation FET's

A novel spectrometer is employed to study the spectrum of heavily doped quantum dots. A single-particle discrete spectrum is found to exist only in close vicinity to the Fermi energy. Levels further away are broadened beyond the average level spacing and merge to form a quasi-continuous spectrum. The broadening is traced to electron-electron interaction in the dot. For the discrete part of the spectrum, level statistics is studied as a function of magnetic field and found to agree remarkably well with recent calculations.

Spectroscopy, Electron-Electron Interaction, and Level Statistics in a Disordered Quantum Dot

Advances in nanolithography using electron‐beam techniques have allowed a great variety of quantum devices to be fabricated and tested. The critical dimensions governing the design of these devices will be discussed. Fabrication and experimental results of several such devices for studies will be reported. These include structures aiming at the observation of the electrostatic Aharonov–Bohm effect and nonlocal oscillations, superconducting weak links, and devices for the investigation of quantum scattering effects.

S. Rishton

Papers

High transconductance and velocity overshoot in NMOS devices at the 0.1- mu m gate-length level

Point exposure distribution measurements for proximity correction in electron beam lithography on a sub‐100 nm scale

Design and experimental technology for 0.1-µm gate-length low-temperature operation FET's

Spectroscopy, Electron-Electron Interaction, and Level Statistics in a Disordered Quantum Dot

Fabrication of quantum devices in metals and semiconductors

S. Rishton

Papers

High transconductance and velocity overshoot in NMOS devices at the 0.1- mu m gate-length level

Point exposure distribution measurements for proximity correction in electron beam lithography on a sub‐100 nm scale

Design and experimental technology for 0.1-&#181;m gate-length low-temperature operation FET's

Spectroscopy, Electron-Electron Interaction, and Level Statistics in a Disordered Quantum Dot

Fabrication of quantum devices in metals and semiconductors

Design and experimental technology for 0.1-µm gate-length low-temperature operation FET's