Showing papers by "Saman Kiamehr published in 2014"
20 Oct 2014
TL;DR: An experimental analysis is made to identify the main parameters and phenomena influencing the performance degradation of FPGAs, and a novel monitoring method based on measuring the electromagnetic emissions of the FPGA is used to accurately monitor the performance of the sensors before and after the stress.
Abstract: Modern Field Programmable Gate Arrays (FPGAs) are built using the most advanced technology nodes to meet performance and power demands. This makes them susceptible to various reliability challenges at nano-scale, and in particular to transistor aging. In this paper, an experimental analysis is made to identify the main parameters and phenomena influencing the performance degradation of FPGAs. For that purpose, a set of controlled ring-oscillator-based sensors with different frequencies and tunable activity control are implemented on a Spartan-6 FPGA. Thus, the internal switching activities (SAs) and signal probabilities (SPs) of the sensors can be varied. We performed accelerated-lifetime conditions using elevated temperatures and voltages in a controlled setting to stress the FPGA. A novel monitoring method based on measuring the electromagnetic emissions of the FPGA is used to accurately monitor the performance of the sensors before and after the stress. The experiments reveal the extent of performance degradations, the impact of SPs and SAs, and the relative impacts of BTI and HCI aging factors.
29 citations
24 Mar 2014
TL;DR: The BTI effect is mitigated by balancing the rise and fall delays of the standard cells at the excepted lifetime by non-uniform extension of the library cells for various ranges of the input signal probabilities.
Abstract: Transistor aging, mostly due to Bias Temperature Instability (BTI), is one of the major unreliability sources at nano-scale technology nodes. BTI causes the circuit delay to increase and eventually leads to a decrease in the circuit lifetime. Typically, standard cells in the library are optimized according to the design time delay, however, due to the asymmetric effect of BTI, the rise and fall delays might become significantly imbalanced over the lifetime. In this paper, the BTI effect is mitigated by balancing the rise and fall delays of the standard cells at the excepted lifetime. We find an optimal tradeoff between the increase in the size of the library and the lifetime improvement (timing margin reduction) by non-uniform extension of the library cells for various ranges of the input signal probabilities. The simulation results reveal that our technique can prolong the circuit lifetime by around 150% with a negligible area overhead.
20 citations
01 Jun 2014
TL;DR: This analysis shows that proton-induced soft errors are becoming important and comparable to the SER induced by alpha-particles especially for low supply voltages (low power applications).
Abstract: This paper presents a comprehensive analysis of radiation-induced soft errors of SRAMs designed in SOI FinFET technology. For this purpose, we propose a cross layer approach starting from a 3D simulation of particle interactions in FinFET structures up to circuit level analysis by considering the layout of the memory array. This approach enables us to consider the effect of different factors such as supply voltage and process variation on Soft Error Rate (SER) of FinFET SRAM memory arrays. Our analysis shows that proton-induced soft errors are becoming important and comparable to the SER induced by alpha-particles especially for low supply voltages (low power applications). Moreover, we observe that the ratio of Multiple Bit Upset (MBU) to Single Event Upset (SEU) for alpha-particle radiation is much higher than that of proton.
19 citations
05 Jan 2014
TL;DR: The proposed Path Healing technique is up to five orders of magnitude faster than Simulated Annealing placement and aims to reduce the total variation of circuit delay using two heuristic placement methods.
Abstract: Carbon Nanotube Field Effect Transistors (CNTFETs) are attractive alternatives to MOSFET devices as CNTFETs benefit from higher on-current, better gate control and faster switching response. However CNTFET-based technologies suffer from higher process variations compared to MOSFET devices. The CNT density variation is one of the most important sources of variation and directly impacts gate delay variation. The density variations of different gates in the layout are asymmetrically correlated according to their positions with respect to CNT growth direction. In this paper, we take advantage of this asymmetric correlation of CNT density to optimize the circuit layout to reduce the total variation of circuit delay using two heuristic placement methods. Simulation results on ISCAS85 Benchmark circuits show a reduction in total delay variation up to 30%. Our proposed Path Healing technique is up to five orders of magnitude faster than Simulated Annealing placement.
5 citations
16 Nov 2014
TL;DR: A fine-grained adaptive technique in which machine learning is exploited to perform circuit clustering and obtain a representative for each cluster, which significantly extends circuit lifetime, facilitates higher operating frequencies, and reduces the leakage power.
Abstract: In the deep nanoscale regime, process and runtime variations have emerged as the major sources of uncertainty and unpredictability in circuit operation. Static mitigation approaches do not consider the dependence of variations on workload and chip usage, while adaptive techniques do not incorporate detailed circuit-level information. We propose a fine-grained adaptive technique in which machine learning is exploited to perform circuit clustering and obtain a representative for each cluster. By monitoring the representative in each cluster at runtime, performance variations in the entire cluster can be tracked such that appropriate fine-grained adaptation can be applied to each cluster. Experimental results for ISCAS'89, IWLS'05, and ITC'99 benchmarks as well as the LEON processor show that the proposed approach introduces negligible overhead significantly extends circuit lifetime, facilitates higher operating frequencies, and reduces the leakage power.