Mini Mental State

Technical foundations introduction software reliability and system reliability the operational profile software reliability modelling survey model evaluation and recalibration techniques practices and experiences best current practice of SRE software reliability measurement experience measurement-based analysis of software reliability software fault and failure classification techniques trend analysis in validation and maintenance software reliability and field data analysis software reliability process assessment emerging techniques software reliability prediction metrics software reliability and testing fault-tolerant SRE software reliability using fault trees software reliability process simulation neural networks and software reliability. Appendices: software reliability tools software failure data set repository.

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Handbook of software reliability engineering

The proliferation of heterogeneous compute platforms, of which CPU/GPU is a prevalent example, necessitates a manageable programming model to ensure widespread adoption. A key component of this is a shared unified address space between the heterogeneous units to obtain the programmability benefits of virtual memory. To this end, we are the first to explore GPU Memory Management Units(MMUs) consisting of Translation Lookaside Buffers (TLBs) and page table walkers (PTWs) for address translation in unified heterogeneous systems. We show the performance challenges posed by GPU warp schedulers on TLBs accessed in parallel with L1 caches, which provide many well-known programmability benefits. In response, we propose modest TLB and PTW augmentations that recover most of the performance lost by introducing L1 parallel TLB access. We also show that a little TLB-awareness can make other GPU performance enhancements (e.g., cache-conscious warp scheduling and dynamic warp formation on branch divergence) feasible in the face of cache-parallel address translation, bringing overheads in the range deemed acceptable for CPUs (10-15\% of runtime). We presume this initial design leaves room for improvement but anticipate that our bigger insight, that a little TLB-awareness goes a long way in GPUs, will spur further work in this fruitful area.

Architectural support for address translation on GPUs: designing memory management units for CPU/GPUs with unified address spaces

This survey exposes the problems related to virtual caches in the context of uniprocessor (Part 1) and multiprocessor (Part 2) systems. We review proposed solutions that have been implemented or proposed in different contexts. The idea is to catalog all solutions, past and present, and to identify technology trends and attractive future approaches. We first overview the relevant properties of virtual memory and of physical caches. To solve the virtual-to-physical address bottle-neck, processors may access caches directly with virtual addresses. This survey introduces the problems and discusses solutions in the context of single-processor systems.

Virtual-address caches. Part 1: problems and solutions in uniprocessors

Most modern cores perform a highly-associative transaction look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it with L1 cache access, but this overlap does not hide the power dissi-pated by TLB lookups. It can even exacerbate the power dissipation by requiring higher associativity L1 cache. With today's concern for power dissipation, designs could instead adopt a virtual L1 cache, wherein TLB access power is dissipated only after L1 cache misses. Unfortunately, virtual caches have compatibility issues, such as supporting writeable synonyms and x86's physical page table walker. This work proposes an Opportunistic Virtual Cache (OVC) that exposes virtual caching as a dynamic optimization by allowing some memory blocks to be cached with virtual addresses and others with physical addresses. OVC relies on small OS changes to signal which pages can use virtual caching (e.g., no writeable synonyms), but defaults to physical caching for compatibility. We show OVC's promise with analysis that finds virtual cache problems exist, but are dynamically rare. We change 240 lines in Linux 2.6.28 to enable OVC. On experiments with Parsec and commercial workloads, the resulting system saves 94-99% of TLB lookup energy and nearly 23% of L1 cache dynamic lookup energy.

/pdf/reducing-memory-reference-energy-with-opportunistic-virtual-13jh74rgo8.pdf

Reducing memory reference energy with opportunistic virtual caching

Agile development methods are being recognized as popular and efficient approaches to the development of software systems that have features such as a short delivery period and unclear requirements. They emphasize customer satisfaction, fast response to changes, and release in less time. According to a recent survey, SCRUM is one of the most popular methods that are currently being used. Some backlogs, especially high priority backlogs that are functional requirements of customers, are developed repeatedly at each sprint period. Despite the known advantages of SCRUM, however, its backlogs focus only on functional features. Thus, it is difficult to effectively reflect the softwares quality attributes. As known, the failure of a software project is caused by the non-satisfaction not of functional features but of quality attributes, such as performance, usability, and reliability. This paper introduces the ACRUM1 that is a quality attribute driven agile development method. The main characteristic of the proposed solution is that it is derived from values and practices of SCRUM to be compatible with the SCRUM process and to keep its agility intact. The effect of ACRUM was evaluated through an agile process evaluation checklist and applying it into a commercial project of Samsung Electronics. The results showed that ACRUM is more efficient than the legacy agile development process.

Quality Attribute Driven Agile Development

Sleep monitoring is vital as sleep plays an important role in recovering physical and mental health. To have a sound sleep, one has to avoid bad sleep positions associated with personal health conditions. However, most of the existing sleep trackers merely show quantitative information about sleep patterns and duration at each sleep stage, overlooking the importance of sleep positions upon sleep quality. To accurately keep track of sleep positions, we propose a wearable sleep position tracking system consisting of two wristbands and one chest-band. We suggest a two-level classifier specialized for sleep motion based on Dynamic State Transition (DST)-framework. The DST-framework is designed to process the spatio-temporal sleep motion data collected via accelerometer/gyro sensing and classify twelve sleep position (SP) motions from four sleep positions. Our experimental results demonstrate that the proposed system effectively and accurately classify twelve SP motions for tracking sleep positions, and hence, serves as a key building block for comprehensive sleep care applications related to sleep positions.

/pdf/a-wearable-sleep-position-tracking-system-based-on-dynamic-4w6uw23lfw.pdf

A wearable sleep position tracking system based on dynamic state transition framework

This paper proposes a cost-effective solution to the synonym problem. In this proposed solution, a minimal hardware addition guarantees the correctness whereas the software counterpart helps improve the performance. The key to this proposed solution is an addition of a small physically-indexed cache called U-cache. The U-cache maintains the reverse translation information of the cache blocks that belong to un-aligned virtual pages only, where aligned means that the lower bits of the virtual page number match those of the corresponding physical page number. A U-cache, even with only one entry, ensures correct handling of synonyms. A simple software optimization in the form of page alignment, helps improve the performance. Performance evaluation based on ATUM traces shows that a U-cache, with only a few entries, performs almost as well as (in some cases outperforms) a fully-configured hardware-based solution when more than 95% of the pages are aligned. >

U-cache: a cost-effective solution to synonym problem

We propose a vector tracking loop (VTL) algorithm for an asynchronous pseudolite navigation system. It was implemented in a software receiver and experiments in an indoor navigation system were conducted. Test results show that the VTL successfully tracks signals against the near-far problem, one of the major limitations in pseudolite navigation systems, and could improve positioning availability by extending pseudolite navigation coverage.

https://www.mdpi.com/1424-8220/10/7/6324/pdf

Implementation of a vector-based tracking loop receiver in a pseudolite navigation system.

Multipath is one of the main error sources in global navigation satellite system (GNSS) positioning. The high-resolution correlator (HRC) is a multipath mitigation technique well known for its outstanding performance for mid-delayed multipath, but still has a remaining error for the short-delayed multipath. This paper proposes a modified HRC scheme that can remove or reduce the error for short-delayed multipath signals. It estimates the HRC tracking error and augments the conventional HRC with the estimates. The method was implemented with a software receiver and the test results show short-delayed multipath-induced errors were reduced to about one third of those from the conventional HRC.

https://www.cambridge.org/core/services/aop-cambridge-core/content/view/S037346330900530X

Sanghoon Jeon

Papers

Quality Attribute Driven Agile Development

A wearable sleep position tracking system based on dynamic state transition framework

U-cache: a cost-effective solution to synonym problem

Implementation of a vector-based tracking loop receiver in a pseudolite navigation system.

Modified High-Resolution Correlator Technique for Short-Delayed Multipath Mitigation