Seiji Kozaki

TL;DR: In this article, a bit identification circuit includes a multiphase clock generation section (121) that outputs multi-phase clocks having a frequency corresponding to the highest bit rate among a plurality of input data signals, phase selection is used to sample input signals using multihase clocks to select a sampled result having the optimum phase from among sampled results, correction means that thins bits of the sampled result selected by the phase selection means on the basis of the difference in bit rate, and a rate selection section (127) that alternatively selects an output of the correction means and an outputof the

TL;DR: A dynamic bandwidth allocation scheme that performs uplink bandwidth allocations in a different manner at every sub-network in order to simultaneously satisfy each sub- network requirement is proposed.

TL;DR: In this paper, a power-saving control unit that intermittently repeats, based on a power saving permission signal transmitted from the master station apparatus, power saving control in which the slave station stops or reduces power supply to a transmitter or a receiver for a predetermined pause duration while maintaining a communication link and a monitoring unit that monitors out of synchronization by comparing a synchronization signal received from the OLT and a time of the ONU.

TL;DR: In this article, a high-speed 82.5 Gsample/s sampling IC and its incorporated burstmode CDR compliant for 10G-EPON systems are presented, which achieved a high pulsewidth distortion tolerance of more than plusmn 0.53 UI under the distorted optical burst packets received condition of BER = 1 times 10 -3.

TL;DR: Experiments show that the scheme can simultaneously provide low-latency transmission, bandwidth guarantee, and auto-discovery process in a converging 5G mobile fronthaul and IoT networks on a TDM-PON.