Showing papers by "Shengdong Zhang published in 2022"
TL;DR: In this paper , an AMOLED pixel circuit based on low-temperature poly-crystalline silicon and oxide (LTPO) thin-film transistors (TFTs) hybrid technology is proposed, which features only two transistors in a serial connection with OLED.
Abstract: In this paper, an AMOLED pixel circuit based on low-temperature poly-crystalline silicon and oxide (LTPO) thin-film transistors (TFTs) hybrid technology is proposed, which features only two transistors in a serial connection with OLED. The power supply can thus be reduced by $25{\sim }30$ % in the “Always-on-Display” (AOD) mode compared with the earlier LTPO pixel circuits which usually have three transistors in the current path and need a higher supply voltage. Furthermore, in addition to a strong suppressing ability to $\text{V}_{\mathrm{ th}}$ variations/shift, the proposed pixel circuit has an excellent compensation ability for current-resistance voltage drops (i.e., IR drop), which is also superior to the earlier LTPO ones where the IR drop has to be compensated externally. Therefore, the proposed LTPO pixel circuit is able to provide AMOLED displays with lower power consumption and higher display performance than the earlier ones.
7 citations
TL;DR: In this article , a room-temperature, solution-processable copper (Cu) electrode is demonstrated to overcome the problem of sintering printed metal particles, which not only will easily damage heat sensitive plastic substrates, but also is difficult to achieve a smooth, neat, and highly adhesive electrode structure.
Abstract: Inkjet‐printed metal electrodes with desirable morphologies and electrical properties are indispensable cornerstones for printable and flexible electronics. However, methods to fabricate metal electrodes nowadays mostly request the sintering of printed metal particles, which not only will easily damage heat‐sensitive plastic substrates, but also is difficult to achieve a smooth, neat, and highly adhesive electrode structure. Herein, a room‐temperature, solution‐processable copper (Cu) electrode is demonstrated to overcome the above issues. The key is to inkjet print a stable xerogel scaffold with high porosity, good uniformity, and smoothness for growing high‐quality Cu via electroless deposition. Xerogel‐based Cu electrodes exhibit a bi‐layer architecture, consisting of an upper thin‐film Cu (with an electrical conductivity of ≈1.2 × 107 S m−1) and a bottom Cu‐polymer interpenetrated network. The electrodes show an excellent uniformity, surface smoothness, high interfacial energy to the plastic substrates (690–970 mJ m−2), and good flexibility. Taking these merits, the electrodes can be patterned onto various plastic substrates and fabricate all‐solution‐processed electronic devices such as organic thin‐film transistors and organic electrochemical transistors with stable electrical performance.
6 citations
01 Jan 2022-Journal of Materials Chemistry C. Materials for Optical, Magnetic and Electronic Devices
TL;DR: In this article , the authors achieved high performance using thin film transistors with low cost, high mobility, and low processing temperature, which are key enablers for practical application.
Abstract: Thin film transistors (TFT) with low cost, high mobility and low processing temperature are key enablers for practical application, which are always contradictory. In this work, we achieved high performance...
6 citations
TL;DR: In this article , the dynamic self-heating degradation was investigated on a-InGaZnO (a-IGZO) thin-film transistors (TFTs) under constant drain bias and varied gate pulses.
Abstract: The dynamic self-heating (SH) degradation was investigated on a-InGaZnO (a-IGZO) thin-film transistors (TFTs) under constant drain bias and varied gate pulses. Besides the negative shift of threshold voltage ( ${V}_{{\mathrm {th}}}$ ), similar with that under DC SH stress, the asymmetric degradations near drain and source revealed the concomitant hot-carrier (HC) effect. The HC-induced local barrier near drain could compensate certain SH-induced ${V}_{{\mathrm {th}}}$ shift, while a drastic SH effect would in turn enhance the HC barrier to high enough to cause hard breakdown. For a-IGZO TFTs under dynamic SH stresses, the interactions between SH and HC effects dominate the degradation behaviors and can be sensitively tuned by the falling time of gate pulse, suggesting a feasible method of lessening the dynamic instability.
5 citations
TL;DR: A fully end-to-end dehazing network, which can be called as dense residual and dilated dehaze network (DRDDN), for single image dehazed, designed to fully exploit multi-scale features through an adaptive learning process.
4 citations
TL;DR: In this article , a hybrid polyimide-Al 2 O 3 material was used as a good gate dielectric to realize truly intrinsic flexibility of transistors and circuits based on CNTs.
Abstract: Abstract The advancement of Internet of Things has stimulated huge demands on low-voltage flexible electronics. Carbon-nanotube (CNT)-based electronics are of great promise to this end for their intrinsic flexibility, high carrier mobility, and capability to synthesize as semiconducting or metallic to serve as the channels, electrodes, and interconnects of circuits. However, the gate dielectric often has to adopt brittle oxides, which can seriously limit the device flexibility. Herein, we show that a hybrid polyimide-Al 2 O 3 material can serve as a good gate dielectric to realize truly intrinsic flexibility of transistors and circuits based on CNTs. With this hybrid dielectric, high-performance all-CNT transistors and integrated circuits of inverters, ring oscillators, and logic gates are demonstrated. Particularly, the inverters exhibit a remarkably high gain of 342.5 and can be used as an analog amplifier for millivolt small signals. Ultralow voltage (50 mV) operation is also feasible, which highlights the great promise for low-power applications.
3 citations
TL;DR: In this article , the authors compared the performance of multilayer AOS TFTs based on amorphous InGaZnO (a•IGZO), amorphou oxide semiconductor (AOS) thin-film transistors (TFTs) and bilayer bilayer, and proposed abrupt metaloxide heterojunction architecture.
Abstract: The large‐area low‐temperature processing capability and versatile characteristics of amorphous oxide semiconductor (AOS) thin‐film transistors (TFTs) are highly expected to promote the developments of next‐generation displays, 3D integrated circuit (3DIC), flexible chips, and electronics. However, the abundant native defects in AOSs engrain an inherent trade‐off between high mobility and trustworthy stability in AOS TFTs, fundamentally limiting the performance metrics and integration scale of oxide‐based electronics. To surmount this obstacle, the bilayer AOS channel is highly expected to combine the merits of diversified AOSs, while the efficiency of such an AOS “heterojunction” is debatable. This work systematically compares the TFTs based on amorphous InGaZnO (a‐IGZO), amorphous InZnO (a‐IZO), and a‐IZO/a‐IGZO bilayer. The active cation interaction between metal‐oxide semiconductors gives rise to a mixed AOS layer rather than a heterojunction channel, corresponding to moderate performance metrics. Such a spontaneous cation interdiffusion is effectively prevented using a dense metal‐oxide dielectric interlayer, aluminum oxide (AlOx). The sharpened interface effectively forms an abrupt metal‐oxide heterojunction, while the electron can still tunnel through the ultrathin AlOx to create a quantum well of 2D electron gas (2DEG). The overall performance and reliability of multilayer AOS TFT are synergistically enhanced using the proposed abrupt metal‐oxide heterojunction architecture.
3 citations
TL;DR: In this article , a scalable polyimide assisted patterning approach for monolithic integration of perovskite based high-sensitive phototransistor array on indium gallium zinc oxide (IGZO) active matrix backplane is introduced.
Abstract: Monolithic integration of perovskite materials and their optoelectronic devices with well‐developed thin‐film transistor (TFT) backplane is leading to new applications in displays and image sensors. Herein, a scalable polyimide assisted patterning approach for monolithic integration of perovskite based high‐sensitive phototransistor array on indium gallium zinc oxide (IGZO) active matrix backplane is introduced. Polyimide vias are first formed by conventional photolithography process, through which uniform perovskite films of arbitrary patterns with feature size less than 20 µm are fabricated by spin‐on‐patterning method. Using this technique, patterns of quasi 2D perovskite photoabsorbing layer are precisely deposited onto the channel area of the photosensing IGZO TFT, forming high‐performance phototransistors with responsivity and detectivity reaching 835.7 A W−1 and 5.4 × 1012 Jones, respectively. An image sensor with 8 × 8 pixels array containing both photosensing perovskite/IGZO transistors and switching IGZO transistors is demonstrated, in which the switching IGZO transistor elements on the backplane are protected by the non‐patterned region of the polyimide encapsulation layer. This whole fabrication process is compatible with TFT manufacturing process and will significantly reduce the cost needed for constructing next generation high‐resolution image sensors.
3 citations
TL;DR: In this article , a dynamic current hysteresis model for the Indium Gallium Zinc Oxide Thin Film Transistor (IGZO-TFT) based on trap kinetics is proposed.
Abstract: • Dynamic current hysteresis that can well capture the effect of the trap energy level, trap density and scan rate is proposed. • This Dynamic current hysteresis model based on trap kinetics is well compatible with SPICE simulations. • The methodology of this hysteresis model can be well extended to other trap kinetics theory and emerging devices. This paper proposes a dynamic current hysteresis model for the Indium Gallium Zinc Oxide Thin Film Transistor (IGZO-TFT). Based on the Shockley-Read-Hall (SRH) theory, a kinetic equation that accurately describes the interface trap’s capture/emission behaviour is presented, which can incorporate the effect of interface trap density, trap energy level and scan rate dependency. Further, the kinetic equation is solved using a sub-circuit approach, combined with a calibrated TFT static current model, to achieve an accurate simulation of the current hysteresis of IGZO-TFT. This model has been validated with numerical TCAD simulations and has been shown to precisely reflect the effect of trap energy level, trap density and scan rate on the current hysteresis characteristics.
2 citations
13 May 2022
TL;DR: In this paper , the effect of inter-electrode coupling on color crosstalk (CCT) of TFT-LCD with high transmittance pixel design is investigated systematically.
Abstract: The effect of inter-electrode coupling on color crosstalk (CCT) of TFT-LCD with high transmittance pixel design is investigated systematically. Theoretical analysis shown that the increased asymmetric capacitive coupling effect between data and pixel electrode signals is the main reason for CCT of the high transmittance panels. If applying some traditional strategies to improve CCT under the line-inversion driving scheme, the effectiveness is very limited and there is a loss of transmittance. When using the proposed sup-flip driving scheme, good image quality with weak CCT can be obtained in the color images. This is mainly ascribed to the dot inversion driving mode of pixel signals, which greatly weakens the coupling effect caused by the change of data signals and balances the brightness difference between adjacent pixels. These results demonstrate that applying the proposed super flip driving scheme is an effective way to modulate the CCT defect and enhance the display performance for TFT-LCDs with high transmittance design.
1 citations
TL;DR: In this paper , a wafer-level flexible fully-carbon-integrated transistors via mixed-dimensional van der Waals (vdW) engineering is realized, and remarkable performance includes subthreshold swing of 51.8 mV dec−1 breaking thermionic limit, outstanding field effect mobility as high as 313.8 cm2 V−1 s−1, and sub-1 V operating voltage.
Abstract: Flexible electronics draw intense interest because of their promising potential for emerging applications, which, however, encounter challenging obstacles of material self‐limiting fabrication, trade‐off mechanical flexibility, and associated moderate electrical performance. Here, wafer‐level flexible fully‐carbon‐integrated transistors via mixed‐dimensional van der Waals (vdW) engineering is realized. Remarkable performance includes subthreshold swing of 51.8 mV dec−1 breaking thermionic limit, outstanding field‐effect mobility as high as 313.8 cm2 V−1 s−1, and sub‐1 V operating voltage. The charge transfer modulation of graphene oxide on carbon nanotube in the vdW‐integrated transistors is designed to enhance channel conductance, which is simultaneously confirmed by theoretical calculations and electrical characterizations. Besides, the transistors maintain stable electrical performance after bending under an ultra‐small radius of 250 µm. Exponential‐sensitivity temperature sensors and binary‐logic inverters are further realized to demonstrate the feasibility of the devices as the building blocks of all‐vdW electronics. These results indicate that either the strategy of all‐vdW transistor realization or the charge transfer provides general approach to improve device performance and further advance flexible electronic technologies.
TL;DR: In this paper , the effect of supercritical carbon dioxide (SCCO2) on both carrier density and carrier transport is investigated using energy band information, Technology Computer Aided Design (TCAD) simulations on density of states and resistance analyses.
Abstract: Amorphous indium gallium zinc oxide (a‐IGZO) thin‐film quality can be enhanced using supercritical carbon dioxide (SCCO2). How to verify specific and accurate mechanism for the carriers inside an a‐IGZO layer before and after the SCCO2 treatment is worth investigating. This work designs a‐IGZO thin film transistors with different channel thicknesses (41, 28, and 19 nm), treats them using SCCO2, and analyzes the change in carrier behavior. The effect of the SCCO2 on both carrier density and carrier transport is investigated using energy band information, Technology Computer Aided Design (TCAD) simulations on density of states and resistance analyses. After the treatment, the thinner channel thickness exhibits better drivability enhancement. That is because of the fewer traps and smoother carrier transportation path resulted from better M−O−M frameworks, and decreased M−OH bonds as well as interface charges. Besides the traditional analysis methods and TCAD simulations, layer‐by‐layer X‐ray photoelectron spectroscopy and sheet resistance measurement are also applied to verify the detailed carrier mechanism behind different phenomena.
TL;DR: In this paper , the degradation and breakdown behaviors of top-gate self-aligned InGaZnO thin-film transistors (TFTs) under dynamic current stresses (DCSs) were systematically investigated.
Abstract: The degradation and breakdown behaviors of top‐gate self‐aligned a‐InGaZnO thin‐film transistors (TFTs) under dynamic current stresses (DCSs) were systematically investigated. Both linear‐ and saturation‐regime DCSs were found to be capable of causing the self‐heating degradations, including the negative shift of threshold voltage, the increase of subthreshold slope and drain current. While the linear DCS eventually forms a conductor‐like channel, the saturation DCS causes an additional hot carrier (HC) effect to form a defective drain regions of high energy barrier, disconnecting the �conductor channel� from the drain side.
18 Nov 2022
TL;DR: In this article , the water-soluble zero-dimension carbon materials, carbon dots (C-dots), were employed as cathode modified layer to enhance the performance of inverted polymer solar cells (PSCs).
Abstract: In this paper, the water-soluble zero-dimension carbon materials, carbon dots (C-dots), were employed as cathode modified layer to enhance the performance of inverted polymer solar cells (PSCs). The results demonstrate C-dots modification can further smooth the surface and decrease the work function of ZnO, thus contributing to the charge extraction and suppressing the charge recombination, and then improve the device efficiency. Besides, the carbon dots covering on ZnO can reduce the directly contact between the ZnO and the NFAs, thereby inhibiting the photocatalytic effect of the ZnO, and moreover, the introduction of the carbon dots enables the electron transport layer interface to have superior energy level contact and higher rectification ratio, which further reduce interface carrier accumulation and recombination, and thus improve the device stability.
TL;DR: In this paper , a pixel circuit with interleaved Emit signals is proposed for active matrix organic light-emitting diode (AMOLED) displays, on the basis of low-temperature polycrystalline silicon oxide (LTPO) TFTs.
Abstract: A concise pixel circuit with interleaved Emit signals is proposed for active matrix organic light‐emitting diode (AMOLED) displays, on the basis of low‐temperature polycrystalline silicon oxide (LTPO) TFTs. The oxide TFT can be re‐used for both initialization and threshold voltage extraction periods, using interleaved Emit signals of adjacent lines with overlapped waveforms. The proposed pixel circuit consists of 1 oxide TFT and 5 p‐type LTPS TFTs, while only 2~3 types of line‐by‐line scanning driving signals, i.e. the Emit signal and the Scan signal, are required. Implementation of the proposed pixel circuit shows that the occupation can be reduced to 40 μm × 56.7 μm. Furthermore, optimization of the pixel circuit shows the emission current error is less than 2.3% with threshold voltage variation of ± 0.5 V, while refresh rate from 1 to 120 Hz can achieved.
23 Sep 2022
TL;DR: In this article , a new shift register based on amorphous Indium-Gallium-Zinc Oxide (IGZO) TFTs for AMOLED with complementary function was proposed.
Abstract: We proposed a new shift register based on amorphous Indium-Gallium-Zinc Oxide (IGZO) TFTs for Active-Matrix Organic Light Emitting Diode (AMOLED) with complementary function. The proposed circuit could steadily output wide pulse and the width can be modulated for threshold voltage compensation which is expected to be applied in high quality AMOLED display. The stability of the circuit has been examined by operating in high temperature and humidity condition exceed 1000 h.
Proceedings Article•
TL;DR: In this article , an exponential dependence of Iph on 1/L was found for TFTs with relatively shorter channels, resulting in a significantly enhanced photo-responsivity with short-channel a-IZO phototransistors.
Abstract: With downscaling the channel length (L) of amorphous InZnO (a-IZO) thin-film transistors (TFTs), the photocurrent (Iph) of long-channel TFTs evolved linearly with 1/L, while an exponential dependence of Iph on 1/L was found for TFTs with relatively shorter channels, resulting in a significantly enhanced photo-responsivity with short-channel a-IZO phototransistors. This is attributed to a source barrier lowering effect happening in the short-channel photo-TFTs under illumination. Such an accelerated Iph rising with L downscaling could be used to implement high responsivity of photoelectric detectors and image sensors.
TL;DR: In this article, a new analytical surfacepotential-based drain current model is presented for the organic thin-film transistors (TFTs) when carriers are confined in two dimensions.
Abstract: A new analytical surface-potential-based drain current model is presented for the organic thin-film transistors (TFTs) when carriers are confined in two dimensions. Following the carrier multiple trapping and release (MTR) conduction theory, i.e., the assumption that the trapped carrier concentration is much higher than the free carrier concentration, the model is developed. The presented model can account for the linear regime and saturation regime by a single formulation. The calculated results of the presented model are verified by the available experimental drain current considering the temperature characteristics. Comparing with the previous model using the variable range hopping and percolation (VRH) conduction theory, although the presented model and the previous model are similar in mathematics, the presented model is more efficient to estimate the density of trap states for the organic TFTs.
15 Feb 2022
TL;DR: A 32×32 pixel avalanche photodiode array read-out circuit is presented in this paper , which adopts a specially designed active-quenching circuit along with function of self-check, auto-reset, and highvoltage protection.
Abstract: A 32×32 pixel avalanche photodiode array read-out circuit is presented. The pixel structure adopts a specially designed active-quenching circuit along with function of self-check, auto-reset, and high-voltage protection. The chip is expected to be used with Avalanche Photodiode (APD) array working at Geiger Mode, and the data of each pixel can be serially output individually in 32 channels. The chip has been fabricated in a 0.18um standard CMOS technology. The pixel pitch is 100um, while the whole chip size is 5 × 6 mm2 which has realized low quenching time of 1ns, high-voltage protection (60V), and minimum time resolution of 500ps.
13 May 2022
TL;DR: In this paper , the authors developed a face seal encapsulation strategy for large-sized flexible top-emission OLEDs, and the lamination process can be used to fabricate them with reduced manufacturing cost and time for mass production.
Abstract: In this paper, the “face seal” encapsulation was developed for large-sized flexible top-emission OLEDs. Before that, the encapsulants including barrier film and UTG were verified to exhibit high performance in the optical properties, mechanical properties and barrier capabilities to moisture, which suggest a promising application in flexible encapsulation. Then, we fabricated four 16.9-inch top-emission OLED panels with different encapsulation structures. It was found that comparing with the pure TFE, the added barrier film shows prolonged RA lifetime at accelerated condition of 85 °C and 85% RH. In addition, the pressure sensitive adhesive (PSA), which attach the encapsulants to the OLED substrates, was inserted with hygroscopic filler to further improve the edge barrier moisture ability, and the RA lifetime was significantly boosted to over 700 h in barrier film based panels. Furthermore, the UTG based panels show the best RA lifetime of over 1000 h. Our research affords a superior “face seal” encapsulation strategy for large-sized flexible top-emission OLEDs, and the lamination process can be used to fabricate them with reduced manufacturing cost and time for mass production.
TL;DR: In this article , a compact integrated gate driver using metal-oxide TFTs is proposed for Micro-LED display, where the positive pulse generation module (i.e. Scan driver) and negative modules (e.g., Emit driver) are located at different side of the micro-LED displays, respectively.
Abstract: A compact integrated gate driver using metal-oxide TFTs is proposed for Micro-LED display. The positive pulse generation module (i.e. Scan driver) and negative modules (i.e. Emit driver) are located at different side of the Micro-LED display, respectively. While Emit signals are re-used for low-level-maintaining of the Scan module, the gate driver design can be much simplified and area occupation of the single gate driver can be reduced to 90 μm(length)× 245 μm(height), while the length of conventional designs exceeds 1000 μm. The simulation results of cascaded gate driver show that the rising time and falling time of the circuit are reduced to 1.3 μs and 2.1 μs, respectively, with the gate loading of 1.5 kΩ and 150 pF.
TL;DR: In this article , a two-mode pulse width modulation (PWM) pixel circuit is proposed for Micro-LED display, which divides the consecutive 8 sub-frames (256 gray levels) into low-bit and high-bit subframes, which are respectively driven by simultaneous emission (SE) and progressive emission (PE) modes.
Abstract: A two-mode pulse width modulation (PWM) pixel circuit is proposed for Micro-LED display. The proposed driving method divides the consecutive 8 sub-frames (256 gray levels) into low-bit and high-bit subframes, which are respectively driven by simultaneous emission (SE) and progressive emission (PE) modes. Compared with the traditional PWM driving scheme, the proposed one shows an increased effective luminous time ratio by 40% for a frame rate of 120Hz, which benefits higher power conversion efficiency. There are only 5 dual-gate metal-oxide transistors for the pixel circuit, while a source-follower structure is adopted to extract the threshold-voltage shift(ΔVth). Simulation results demonstrate that the current error rates can be reduced to 2% with ΔVth of ± 1 V for various grayscales.
TL;DR: In this article , a thin-film transistors (TFTs) integrated gate driver which can work well at low temperature down to $- 40\,\,^{\circ} \text{C}$ ,
Abstract: A thin-film transistors (TFTs) integrated gate driver which can work well at low temperature down to $- 40\,\,^{\circ} \text{C}$ is proposed and demonstrated. The carry signal (CN) of the driver, being generated through the voltage bootstrapping approach using a CN-connected capacitor, is used to pre-charge the following stage of the driver. As the rising and falling time of CN is much shorter than that of the gate driving signal GN, the bootstrapping voltage is increased and voltage loss of the pre-charge transistor can be much reduced, to avoid the driver’s malfunction at low temperature. This structure further benefits maintaining the driving speed over long operation time at high temperature. On the other hand, the GN, instead of CN, is used to reset the gate driver to suppress the voltage feed-through effects. One single stage of the driver consists of 11 TFTs and 2 capacitors, driven by 4 clock signals with the duty ratio of 25%. An a-Si:H TFTs implemented single stage circuit of the driver occupies an area of 250 $\mu \text{m}\times 1099\,\,\mu \text{m}$ . Measurements show that the output voltage magnitude can be maintained well when temperature varies from $- 40\,\,^{\circ} \text{C}$ to 80 °C. Moreover, the rising-time and falling-time increase of the output pulse are both less than $3~\mu \text{s}$ after 240 hours of the accelerated high temperature aging operations.