In this paper, the metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology is reviewed. The technology offers several benefits that enable scaling to sub-30-nm gate lengths including extremely low parasitic S/D resistance (1% of the total device resistance), atomically abrupt junctions that enable the physical scaling of the device to sub-10-nm gate lengths, superior control of OFF-state leakage current due to the intrinsic Schottky potential barrier, and elimination of parasitic bipolar action. These and other benefits accrue using a low-thermal-budget CMOS manufacturing process requiring two fewer masks than conventional bulk CMOS. The SB-CMOS manufacturing process enables integration of critical new materials such as high-k gate insulators and strained silicon substrates. SB MOSFET technology state of the art is also reviewed, and shown to be focused on barrier-height-lowering techniques that use interfacial layers between the metal S/Ds and the channel region. SB-PMOS devices tend to have superior performance compared to NMOS, but NMOS performance has recently improved by using ytterbium silicide or by using hybrid structures that incorporate interfacial layers to lower the SB height.

Overview and status of metal S/D Schottky-barrier MOSFET technology

We propose and theoretically analyze a metal–oxide–semiconductor field-effect-transistor (MOSFET) type of spin transistor (spin MOSFET) consisting of a MOS structure and half-metallic-ferromagnet (HMF) contacts for the source and drain. When the magnetization configuration of the HMF source and drain is parallel (antiparallel), highly spin-polarized carriers injected from the HMF source to the channel are transported into (blocked by) the HMF drain, resulting in the magnetization-configuration-dependent output characteristics. Our two-dimensional numerical analysis indicates that the spin MOSFET exhibits high (low) current drive capability in the parallel (antiparallel) magnetization, and that extremely large magnetocurrent ratios can be obtained. Furthermore, the spin MOSFET satisfies other important requirements for “spintronic integrated circuits,” such as high amplification capability, low power-delay product, and low off-current.

A spin metal–oxide–semiconductor field-effect transistor using half-metallic-ferromagnet contacts for the source and drain

Metal silicides have played an indispensable role in the rapid developments of microelectronics since PtSi was first used to improve the rectifying characteristics of diodes in early 1960s. This wo ...

Metal silicides in CMOS technology : Past, present, and future trends

Ytterbium silicide, for the first time, was used to form the Schottky barrier source/drain (S/D) of N-channel MOSFETs. The device fabrication was performed at low temperature, which is highly preferred in the establishment of Schottky barrier S/D transistor (SSDT) technology, including the HfO/sub 2/ gate dielectric, and HaN/TaN metal gate. The YbSi/sub 2 - x/ silicided N-SSDT has demonstrated a very promising characteristic with a recorded high I/sub on//l/sub off/ ratio of /spl sim/10/sup 7/ and a steep subthreshold slope of 75 mV/dec, which is attributed to the lower electron barrier height and better film morphology of the YbSi/sub 2 - x//Si contact compared with other self-aligned rare earth metal-(Erbium, Terbium, Dysprosium) silicided Schottky junctions.

https://ir.nctu.edu.tw:443/bitstream/11536/26516/1/000222905100017.pdf

N-type Schottky barrier source/drain MOSFET using ytterbium silicide

Schottky-barrier source/drain (S/D) germanium p-channel MOSFETs are demonstrated for the first time with HfAlO gate dielectric, HfN-TaN metal gate and self-aligned NiGe S/D. The drain drivability is improved over the silicon counterpart with PtSi S/D by as much as /spl sim/5 times due to the lower hole Schottky barrier of the NiGe-Ge contact than that of PtSi-Si contact as well as the higher mobility of Ge channel than that of Si.

https://ir.nctu.edu.tw:443/bitstream/11536/23688/1/000226479100011.pdf

Germanium pMOSFETs with Schottky-barrier germanide S/D, high-/spl kappa/ gate dielectric and metal gate

The Schottky source/drain metal-oxide-semiconductor field-effect transistor (MOSFET) has potential for scaling to the nanometer regime, because low electrode resistances with very shallow extension can be realized using metal source/drain. In this study, very short channel n- and p-type Schottky source/drain MOSFETs with silicon-on-insulator (SOI) structure were analyzed theoretically, and n-type devices were demonstrated experimentally. It was shown theoretically that a drivability of the Schottky source/drain MOSFET comparable to that of conventional MOSFETs can be realized with a low Schottky barrier height. The short-channel effect can be suppressed even with a 15-nm-long channel at tOX = 1 nm and tSOI = 3 nm. The room-temperature operation of sub-50-nm n-type ErSi2 Schottky source/drain MOSFETs on a separation by implanted oxygen (SIMOX) substrate was demonstrated.

https://iopscience.iop.org/article/10.1143/JJAP.38.6226/pdf

Analysis of Short-Channel Schottky Source/Drain Metal-Oxide-Semiconductor Field-Effect Transistor on Silicon-on-Insulator Substrate and Demonstration of Sub-50-nm n-type Devices with Metal Gate

P-type metal oxide semiconductor field-effect transistors with PtSi Schottky sources/drains with a 35-nm long metal gate were fabricated on a separation by implanted oxygen substrate by electron-beam lithography and a self-aligned silicide process. The drain current was -176 µA/µm and the transconductance was 390 mS/mm at VDS = VGS = -1.5 V. For these devices, comparable drivability to conventional metal oxide semiconductor field-effect transistors was achieved. The on/off ratio was improved using a very thin silicon-on-insulator structure.

https://iopscience.iop.org/article/10.1143/JJAP.38.L629/pdf

35 nm Metal Gate p-type Metal Oxide Semiconductor Field-Effect Transistor with PtSi Schottky Source/Drain on Separation by Implanted Oxygen Substrate

A buried metal heterojunction bipolar transistor with a 05-µm-wide emitter was fabricated by electron-beam lithography, in which three tungsten wires of 100 nm width, 100 nm height and 200 nm period were buried in the InP collector layer For the device with an emitter area of 05×25 µm2, total base-collector capacitance was reduced to about 30% of that calculated from the physical dimensions of a conventional heterojunction bipolar transistor, and a current gain cutoff frequency of 86 GHz and a maximum oscillation frequency higher than 135 GHz were obtained

http://www.pe.titech.ac.jp/~miya/result/Publication/jjap_v40_2001_l735.pdf

Reduction of Base-Collector Capacitance in Submicron InP/GaInAs Heterojunction Bipolar Transistors with Buried Tungsten Wires

We report a novel approach for improving the performance of InP-based heterojunction bipolar transistors (HBTs). A buried-metal heterojunction bipolar transistor (BM-HBT), in which tungsten stripes of the same area as the emitter metal were buried in an i-InP collector layer, was fabricated for the first time. The aim in fabricating this structure is to realize a reduction in the total base-collector capacitance (CBCT). In the measurement of microwave S-parameters, CBCT of 10.3 fF was evaluated. The effective base-collector junction area of the BM-HBT was estimated to be 22% that of conventional-HBT considering the difference in collector thickness.

/pdf/first-fabrication-of-gainas-inp-buried-metal-heterojunction-8wc61nnmpe.pdf

Shigeharu Yamagami

Papers

Analysis of Short-Channel Schottky Source/Drain Metal-Oxide-Semiconductor Field-Effect Transistor on Silicon-on-Insulator Substrate and Demonstration of Sub-50-nm n-type Devices with Metal Gate

35 nm Metal Gate p-type Metal Oxide Semiconductor Field-Effect Transistor with PtSi Schottky Source/Drain on Separation by Implanted Oxygen Substrate

Reduction of Base-Collector Capacitance in Submicron InP/GaInAs Heterojunction Bipolar Transistors with Buried Tungsten Wires

First Fabrication of GaInAs/InP Buried Metal Heterojunction Bipolar Transistor and Reduction of Base-Collector Capacitance