An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by a switching control voltage (SW) or its inverse (SW_), which are approximately symmetrical about ground. The transistor groupings each comprise one or more insulating gate FET transistors connected together in a “stacked” series channel configuration, which increases the breakdown voltage across the series connected transistors and improves RF switch compression. A fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements. In one embodiment, the fully integrated RF switch includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.

Switch Circuit and Method of Switching Radio Frequency Signals

Intrinsic threshold voltage fluctuations introduced by local oxide thickness variations (OTVs) in deep submicrometer (decanano) MOSFETs are studied using three-dimensional (3-D) numerical simulations on a statistical scale. Quantum mechanical effects are included in the simulations employing the density gradient (DG) formalism. The random Si/SiO/sub 2/ and gate/SiO/sub 2/ interfaces are generated from a power spectrum corresponding to the autocorrelation function of the interface roughness. The impact on the intrinsic threshold voltage fluctuations of both the parameters used to reconstruct the random interface and the MOSFET design parameters are studied using carefully designed simulation experiments. The simulations show that intrinsic threshold voltage fluctuations induced by local OTV become significant when the dimensions of the devices become comparable to the correlation length of the interface. In MOSFETs with characteristic dimensions below 30 nm and conventional architecture, they are comparable to the threshold voltage fluctuations introduced by random discrete dopants.

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Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF− terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device

A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal. A preferred embodiment of the RF transceiver IC includes two distinct PA circuits, two distinct receive signal amplifier circuits, and a four-way antenna switch to selectably couple a single antenna connection to any one of the four circuits.

Integrated RF front end with stacked transistor switch

Preface. Acknowlegments. Introduction. SOI CMOS Devices--Part I. SOI CMOS Devices--Part II. Fundamentals of SOI CMOS Circuits. SOI CMOS Digital Circuits. SOI CMOS Analog Circuits. PD SOI-Technology SPICE Models. Index.

Low-Voltage SOI CMOS VLSI Devices and Circuits

This paper reports an analytical inverse narrow-channel effect threshold voltage model for shallow-trench-isolated (STI) CMOS devices using a conformal mapping technique to simplify the two-dimensional (2-D) analysis. As verified by the experimentally measured data and the 2-D simulation results, the analytical model predicts well the inverse narrow-channel effect threshold voltage behavior of the STI CMOS devices. Based on the study, the inverse narrow-channel effect also affects the saturation-region output conductance of a small geometry STI CMOS device in addition to the short-channel effect.

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A closed-form back-gate-bias related inverse narrow-channel effect model for deep-submicron VLSI CMOS devices using shallow trench isolation

This paper presents a closed-form threshold-voltage model for short-channel partially-depleted (PD) SOI dynamic-threshold MOS (DTMOS) devices based on a quasi-two-dimensional (2-D) approach. As verified by experimental data and 2-D simulation results, this compact model provides an accurate prediction of the threshold-voltage behavior of the short-channel PD SOI DTMOS devices. Based on the analytical model, as verified by the 2-D simulation results, PD SOI DTMOS devices have less short-channel effects including DIBL-induced short-channel effects as compared to the devices without the DTMOS configuration.

Compact threshold-voltage model for short-channel partially-depleted (PD) SOI dynamic-threshold MOS (DTMOS) devices

This paper reports an analytical subthreshold current hump model for deep-submicron shallow-trench-isolated CMOS devices. As verified by the experimental data, this subthreshold current hump model can provide a prediction of the back gate bias related subthreshold current hump phenomenon. According to the analytical model, with a more heavily doped substrate, the current hump phenomenon occurs at a more negative back gate bias.

Analytical subthreshold current hump model for deep-submicron shallow-trench-isolated CMOS devices

This paper reports a closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted (FD) SOI NMOS devices with lightly-doped drain (LDD) structure. As verified by the two-dimensional (2-D) simulation results, the analytical drain current model considering energy transport and self-heating provides an accurate prediction of the drain current behavior of the 0.25-/spl mu/m FD SOI NMOS device with and without an LDD structure. From the analytical model, with the LDD structure, the device has a smaller effective electron mobility at a low drain voltage, where lattice temperature is dominant, and a higher effective mobility at a high drain voltage, where electron temperature dominates, as compared to the non-LDD device.

Closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted SOI NMOS devices with lightly-doped drain structure biased in strong inversion

Shih-Chia Lin

Papers

Low-Voltage SOI CMOS VLSI Devices and Circuits

A closed-form back-gate-bias related inverse narrow-channel effect model for deep-submicron VLSI CMOS devices using shallow trench isolation

Compact threshold-voltage model for short-channel partially-depleted (PD) SOI dynamic-threshold MOS (DTMOS) devices

Analytical subthreshold current hump model for deep-submicron shallow-trench-isolated CMOS devices

Closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted SOI NMOS devices with lightly-doped drain structure biased in strong inversion