As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of VLSI systems. This paper defines noise as it pertains to digital systems and addresses the technology trends which are bringing noise issues to the forefront. The noise sources which are plaguing digital systems are explained. A metric referred to as noise stability is defined, and a static noise analysis methodology based on this metric is introduced to demonstrate how noise can be analyzed systematically. Analysis issues associated with on-chip interconnect are also considered. This paper concludes with a discussion of the device, circuit, layout, and logic design issues associated with noise.

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Noise in deep submicron digital design

A semiconductor memory device includes a memory cell array having a first group of main blocks, a second group of main blocks and redundancy blocks replacing the first group of main blocks or the second group of main blocks, a repair logic suitable for enabling a replacement signal when one or more of the second group of main blocks are defective, a control logic suitable for generating an address for the second group of main blocks in response to a dedicated command for access to one or more of the second group of main blocks, and an address decoder suitable for selecting one or more of the redundancy blocks based on the address for the second group of main blocks when the replacement signal is enabled.

Semiconductor memory device and method of operating the same

This work analyzes both by simulations and measurements the substrate crosstalk performances of various Silicon-On-Insulator (SOI) technologies, and compares them to those of normal bulk CMOS process. The influence of various parameters, such as substrate resistivity, buried oxide thickness and distance between devices, is investigated. The use of capacitive guard rings is proposed, and their effectiveness is demonstrated. A simple RC model has been developed to allow a deep understanding of these phenomena as well as to simplify future studies of more complex systems. The superiority of high-resistivity SIMOX substrates over standard SOI and bulk is finally demonstrated.

Substrate crosstalk reduction using SOI technology

This paper describes a fast and accurate simulator for characterizing the effects of substrate coupling on integrated-circuit performance. The technique uses the electrostatic Green function of the substrate medium and the fast Fourier transform algorithm. It is demonstrated that this technique is suitable for optimization of layout for minimization of substrate coupling. Analysis of substrate coupling in different types of substrates and the utility of guard rings in different types of substrates is also discussed. Experimental verification of the models is presented.

Modeling and analysis of substrate coupling in integrated circuits

In this paper, a 14-bit, 150-MSamples/s current steering digital-to-analog converter (DAC) is presented. It uses the novel Q/sup 2/ random walk switching scheme to obtain full 14-bit accuracy without trimming or tuning. The measured integral and differential nonlinearity performances are 0.3 and 0.2 LSB, respectively; the spurious-free dynamic range is 84 dB at 500 kHz and 61 dB at 5 MHz. Running from a single 2.7-V power supply, it has a power consumption of 70 mW for an input signal of 500 kHz and 300 mW for an input signal of 15 MHz. The DAC has been integrated in a standard digital single-poly, triple-metal 0.5-/spl mu/m CMOS process. The die area is 13.1 mm/sup 2/.

A 14-bit intrinsic accuracy Q/sup 2/ random walk CMOS DAC

A radio frequency identification tag LSI operating with the carrier frequency of 13.56MHz as well as storing nonvolatile information in embedded ferroelectric random access memory (FeRAM) has been developed. A full wave rectifier composed of PMOS transistor diodes and NMOS transistor switches achieves RF-to-DC power conversion efficiency over 54%. The entire 16 kbits write and read transaction time can be reduced to 2.1 sec by the use of FeRAM, which corresponds to 2.2 times speed enhancement over conventional EEPROM based tag LSIs. The communication range of the FeRAM based tag LSI can be effectively improved by storing antitheft information in a ferroelectric nonvolatile flip-flop, which can reduce the power consumption of FeRAM from 27μW to 5μW. The communication range for the antitheft gate system becomes 70 cm.

A 13.56 MHz CMOS RF Identification Passive Tag LSI with Ferroelectric Random Access Memory

An integrated circuit has a sleep switch, provided between a first power line and a second power line, which is constituted by a transistor of a first threshold voltage, and which becomes non-conducting in a sleep mode, and further has a latch circuit, connected to the second power line, which is constituted by a transistor of a second threshold voltage which is lower than the first threshold voltage, and a ferroelectric capacitor for storing data held in the latch circuit in accordance with the polarization direction of a ferroelectric film thereof. The integrated circuit also comprises a control signal generating circuit which, when returning to an active mode from the sleep mode, generates a plate signal for driving a terminal of the ferroelectric capacitor to generate a voltage in the latch circuit in accordance with the polarization direction, and generates a sleep signal for causing the sleep switch to conduct to thereby activate the latch circuit following the driving of the ferroelectric capacitor.

Multi-threshold-voltage integrated circuit having a non-volatile data storage circuit

Integrated circuit having nonvolatile data storage circuit

PROBLEM TO BE SOLVED: To simplify power source wiring, to make an integration degree high and to stabilize the operation of a latch circuit in returning from a sleep mode, in an MTCMOS integrated circuit device. SOLUTION: An integrated circuit device is provided between normal power source wiring Vdd and virtual power source wiring VVdd, is composed of a high threshold voltage transistor and has a sleep switch SSW that becomes nonconductive. In addition, the integrated circuit device has the latch circuit 14 connected to the virtual power source wiring VVdd and composed of a low threshold voltage transistor, and a ferroelectric capacitor for storing data held by the latch circuit. A control signal generation circuit 5 generates a plate signal PL that drives a terminal of the ferroelectric capacitor and generates voltage in the latch circuit in accordance with a polarization direction and a sleep signal SLP that makes the sleep switch SSW conductive after the terminal is driven to activate the latch circuit 14 in returning to an active mode from the sleep mode. That is, the sleep switch SSW performs sleep control and activation control of the latch circuit. COPYRIGHT: (C)2004,JPO

Integrated circuit device having a nonvolatile data storage circuit

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits (Special Section on the 1992 VLSI Circuits Symposium)

Shoichi Masui

Papers

A 13.56 MHz CMOS RF Identification Passive Tag LSI with Ferroelectric Random Access Memory

Multi-threshold-voltage integrated circuit having a non-volatile data storage circuit

Integrated circuit having nonvolatile data storage circuit

Integrated circuit device having a nonvolatile data storage circuit

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits (Special Section on the 1992 VLSI Circuits Symposium)