As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of VLSI systems. This paper defines noise as it pertains to digital systems and addresses the technology trends which are bringing noise issues to the forefront. The noise sources which are plaguing digital systems are explained. A metric referred to as noise stability is defined, and a static noise analysis methodology based on this metric is introduced to demonstrate how noise can be analyzed systematically. Analysis issues associated with on-chip interconnect are also considered. This paper concludes with a discussion of the device, circuit, layout, and logic design issues associated with noise.

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Noise in deep submicron digital design

A semiconductor memory device includes a memory cell array having a first group of main blocks, a second group of main blocks and redundancy blocks replacing the first group of main blocks or the second group of main blocks, a repair logic suitable for enabling a replacement signal when one or more of the second group of main blocks are defective, a control logic suitable for generating an address for the second group of main blocks in response to a dedicated command for access to one or more of the second group of main blocks, and an address decoder suitable for selecting one or more of the redundancy blocks based on the address for the second group of main blocks when the replacement signal is enabled.

Semiconductor memory device and method of operating the same

This work analyzes both by simulations and measurements the substrate crosstalk performances of various Silicon-On-Insulator (SOI) technologies, and compares them to those of normal bulk CMOS process. The influence of various parameters, such as substrate resistivity, buried oxide thickness and distance between devices, is investigated. The use of capacitive guard rings is proposed, and their effectiveness is demonstrated. A simple RC model has been developed to allow a deep understanding of these phenomena as well as to simplify future studies of more complex systems. The superiority of high-resistivity SIMOX substrates over standard SOI and bulk is finally demonstrated.

Substrate crosstalk reduction using SOI technology

This paper describes a fast and accurate simulator for characterizing the effects of substrate coupling on integrated-circuit performance. The technique uses the electrostatic Green function of the substrate medium and the fast Fourier transform algorithm. It is demonstrated that this technique is suitable for optimization of layout for minimization of substrate coupling. Analysis of substrate coupling in different types of substrates and the utility of guard rings in different types of substrates is also discussed. Experimental verification of the models is presented.

Modeling and analysis of substrate coupling in integrated circuits

In this paper, a 14-bit, 150-MSamples/s current steering digital-to-analog converter (DAC) is presented. It uses the novel Q/sup 2/ random walk switching scheme to obtain full 14-bit accuracy without trimming or tuning. The measured integral and differential nonlinearity performances are 0.3 and 0.2 LSB, respectively; the spurious-free dynamic range is 84 dB at 500 kHz and 61 dB at 5 MHz. Running from a single 2.7-V power supply, it has a power consumption of 70 mW for an input signal of 500 kHz and 300 mW for an input signal of 15 MHz. The DAC has been integrated in a standard digital single-poly, triple-metal 0.5-/spl mu/m CMOS process. The die area is 13.1 mm/sup 2/.

A 14-bit intrinsic accuracy Q/sup 2/ random walk CMOS DAC

A Judging Support System for Gymnastics Using 3D Sensing and Element Recognition

We explore a dual-band fractional-N PLL synthesizer with 3.5mW, 5µsec settling time and 15µsec start-up time in 0.18µm CMOS technology. The power consumption is minimized through the design efforts in LC-VCO design to maximize the quality factor of an integrated inductor up to 6.1 at 866MHz and minimize the VCO gain by a capacitor tuning technique with an on-chip nonvolatile memory and the proper choice of varactor. Measured results of a prototype fractional-N PLL satisfy the required settling and start-up times, and indicate that the phase noises at 10kHz and 100KHz offset are -108.7dBc/Hz and -98.3dBc/Hz, respectively, and the reference spurious level is -81.6dBc.

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A 3.5mW 5µsec settling time dual-band fractional-N PLL synthesizer

According to the present invention, a recognition device acquires skeleton information in time series, the skeleton information being based on the position information of each of a plurality of joints including a specific joint of a subject doing exercise. The recognition device also estimates, using the position information of the plurality of joints included in the respective time-series skeleton information, an area in which the specific joint is located, among a plurality of areas into which the area of an object used in exercise is divided. Thereafter, the recognition device recognizes the exercise of the subject by using the time-series skeleton information and the estimated position of the specific joint, and outputs the recognition result.

Exercise recognition method, exercise recognition program, and information processing device

SPICE MOSFET Analog Model Parameter Verification and Re-optimization Based on g m /I D Lookup Table Design Methodology

Selon l'invention, parmi une multitude d'etiquettes electroniques, seule celle qui contient des donnees concordant avec une condition participe a une operation anti-collision, accelerant ainsi la detection de l’etiquette electronique qui contient des donnees concordantes. L’etiquette electronique comprend un moyen de stockage des donnees a envoyer et un moyen pour comparer les donnees stockees aux donnees de comparaison envoyees par un lecteur/enregistreur et permettant ainsi de definir en tant qu’operation necessaire avant l’envoi de donnees au lecteur/enregistreur si l’identificateur de sa propre etiquette doit ou non etre envoye de facon a participer a l’operation anti-collision a effectuer entre le lecteur/enregistreur.

Shoichi Masui

Papers

A Judging Support System for Gymnastics Using 3D Sensing and Element Recognition

A 3.5mW 5µsec settling time dual-band fractional-N PLL synthesizer

Exercise recognition method, exercise recognition program, and information processing device

SPICE MOSFET Analog Model Parameter Verification and Re-optimization Based on g m /I D Lookup Table Design Methodology

Étiquette électronique et système d’étiquette électronique