An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer Observations indicate that reducing the inductance in the substrate bias is the most effective Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed >

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits

A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18-20 dB of maximum gain and 3-3.5 dB of noise figure over 800 MHz to 6 GHz. A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around +70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards

An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS

As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of VLSI systems. This paper defines noise as it pertains to digital systems and addresses the technology trends which are bringing noise issues to the forefront. The noise sources which are plaguing digital systems are explained. A metric referred to as noise stability is defined, and a static noise analysis methodology based on this metric is introduced to demonstrate how noise can be analyzed systematically. Analysis issues associated with on-chip interconnect are also considered. This paper concludes with a discussion of the device, circuit, layout, and logic design issues associated with noise.

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Noise in deep submicron digital design

CMOS Data Converters for Communications distinguishes itself from other data converter books by emphasizing system-related aspects of the design and frequency-domain measures. It explains in detail how to derive data converter requirements for a given communication system (baseband, passband, and multi-carrier systems). The authors also review CMOS data converter architectures and discuss their suitability for communications. The rest of the book is dedicated to high-performance CMOS data converter architecture and circuit design. Pipelined ADCs, parallel ADCs with an improved passive sampling technique, and oversampling ADCs are the focus for ADC architectures, while current-steering DAC modeling and implementation are the focus for DAC architectures. The principles of the switched-current and the switched-capacitor techniques are reviewed and their applications to crucial functional blocks such as multiplying DACs and integrators are detailed. The book outlines the design of the basic building blocks such as operational amplifiers, comparators, and reference generators with emphasis on the practical aspects. To operate analog circuits at a reduced supply voltage, special circuit techniques are needed. Low-voltage techniques are also discussed in this book. CMOS Data Converters for Communications can be used as a reference book by analog circuit designers to understand the data converter requirements for communication applications. It can also be used by telecommunication system designers to understand the difficulties of certain performance requirements on data converters. It is also an excellent resource to prepare analog students for the new challenges ahead.

CMOS Data Converters for Communications

This work analyzes both by simulations and measurements the substrate crosstalk performances of various Silicon-On-Insulator (SOI) technologies, and compares them to those of normal bulk CMOS process. The influence of various parameters, such as substrate resistivity, buried oxide thickness and distance between devices, is investigated. The use of capacitive guard rings is proposed, and their effectiveness is demonstrated. A simple RC model has been developed to allow a deep understanding of these phenomena as well as to simplify future studies of more complex systems. The superiority of high-resistivity SIMOX substrates over standard SOI and bulk is finally demonstrated.

Substrate crosstalk reduction using SOI technology

An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer. Observations indicate that reducing the inductance in the substrate bias is the most effective. Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry. A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed. >

Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits

Oversampling digital-to-analog (D/A) converters employing sigma-delta modulation noise shaping and single-bit quantization are attractive for use in digital audio applications because of their relaxed reconstruction filtering requirements and their tolerance of component mismatch. However, the use of a two-level D/A interface results in a large amount of out-of-band quantization noise that typically must be attenuated by a carefully designed analog reconstruction filter. This paper introduces a means of simplifying the reconstruction filter design through the use of a semidigital finite-impulse-response (FIR) filter. In particular, it describes an oversampling D/A converter wherein a current-mode semidigital reconstruction filter is used to implement a multilevel D/A interface that attenuates the out-of-band quantization noise without requiring precise component matching. An experimental implementation of the converter achieves a dynamic range of 94 dB and 72 dB attenuation of out-of-band quantization noise for a baseband of 20 kHz. The prototype converter, which consists of a linear interpolator, a second-order noise shaper, and a 128-tap semidigital FIR filter, dissipates 59 mW from a 5-V supply and occupies an active area of 3 mm/sup 2/ when integrated in a 1.2- mu m digital CMOS technology. >

A CMOS oversampling D/A converter with a current-mode semi-digital reconstruction filter

A single-chip dual-band tri-mode CMOS transceiver that implements the RF and analog front-end for an IEEE 802.11a/b/g wireless LAN is described. The chip is implemented in a 0.25-/spl mu/m CMOS technology and occupies a total silicon area of 23 mm/sup 2/. The IC transmits 9 dBm/8 dBm error vector magnitude (EVM)-compliant output power for a 64-QAM OFDM signal. The overall receiver noise figure is 5.5/4.5 dB at 5 GHz/2.4 GHz. The phase noise is -105 dBc/Hz at a 10-kHz offset and the spurs are below -64 dBc when measured at the 5-GHz transmitter output.

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A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN

The influence of substrate noise coupling on the performance of a low-noise amplifier (LNA) for a CMOS GPS receiver has been investigated both analytically and experimentally. A frequency-domain approach has been used to model both noise injection into the substrate from digital circuitry integrated on the same chip and the mechanisms by which that noise can affect analog circuit behavior. The results of this study reveal that substrate noise can modulate the LNA input signal as well as couple directly to the amplifier's output.

David K. Su

Papers

Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits

A CMOS oversampling D/A converter with a current-mode semi-digital reconstruction filter

A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN

Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver