2.5D packages have been widely used in electronics industry for high performance and product miniaturization. As Through-Silicon-Via (TSV) fabrication methods and multi-level assembly technologies get mature, 2.5D packaging becomes reliable and affordable. In this work, board-level life prediction was performed for a 2.5D Field-Programmable Gate Array (FPGA) assembly in both accelerated thermal cycling and power cycling. Finite element models were built and validated by warpage measurement. Solder fatigue life in power cycling was investigated by computational fluid dynamics (CFD) simulation and finite element analysis. Improved life prediction for power cycling was achieved by mapping temperature results from CFD model to finite element model. Parametric studies regarding geometry and material factors were performed including PCB, substrate, thermal interface material (TIM) and lid adhesive, to give design suggestions to improve board-level thermal reliability. Maximum junction temperature of a 2.5D FPGA package is dependent on application scenarios and working environment. It is found that the designed maximum junction temperature and applied heatsink clamping force have considerable influences on board-level reliability.

Comprehensive Study on 2.5D Package Design for Board-Level Reliability in Thermal Cycling and Power Cycling

This paper considers the problem of delay-independent stabilization of linear fractional order (FO) systems with state delay. As in most practical systems in which the value of delay is not exactly...

Delay-independent sliding mode control of time-delay linear fractional order systems:

A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for nicker (1/f) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit. This is validated by simulation and measurement. Straightforward expressions for period jitter and phase noise enable manual design of a ring oscillator to specifications, and guide the choice between ring and LC oscillator.

Phase noise and jitter in CMOS ring oscillators

Summary
This paper presents a novel second-generation current conveyor (CCII)-based non-inverting Schmitt trigger topology. By means of the use of only three resistances, it is possible to set easily the threshold values or, in addition, the trigger can be set also to work as a zero-voltage comparator. The theoretical working principle has been confirmed through PSpice simulations implementing an integrated CCII, designed in a low-cost standard complementary metal–oxide–semiconductor technology (Austria Micro Systems (AMS) 0.35 µm) with low-voltage low-power characteristics, and then by experimental tests on the fabricated printed circuit board prototype through the use of the commercial component AD844 (Analog Devices) as CCII. As its main application example, the presented trigger has been employed to implement an astable multivibrator proposed here as a capacitive sensor interface capable to accurately detect about five decades of capacitive variations in the range of [100 pF–5.5 μF] with a maximum relative error lower than ±10%. Copyright © 2016 John Wiley & Sons, Ltd.

A CCII‐based non‐inverting Schmitt trigger and its application as astable multivibrator for capacitive sensor interfacing

In this paper, the authors present two topologies of voltage mode third order quadrature oscillator circuit using operational transresistance amplifier (OTRA). The first circuit is based on low-pass filter and integrator combination, whereas the second one is high-pass filter and differentiator combination. Both the circuits utilize two OTRAs and three resistors and capacitors each. The frequency of oscillation and condition of oscillation can be adjusted independent of each other in both the circuits. The non-ideality analysis of the circuits are also included. The PSPICE simulation and experimental results verify the theoretical proposition.

Voltage mode third order quadrature oscillators using OTRAs

This paper presents an all-digital self-calibrated delay-line based temperature sensor. A continuous self-calibration technique is proposed to remove process variations and to generate direct digital representations of temperature. A power saving scheme using a hybrid counter/pulse position decoder is also introduced without any increase in area overhead. Four different architectures including traditional long and short delay-lines, and the proposed power saving hybrid sensor with long and short delay-lines are implemented on multiple 65nm Cyclone III FPGAs along with an on-chip continuous self-calibration circuit. The logic utilization for a single sensor is as small as 60 Logic Elements (LE) and its measured power consumption is as low as 2.9 μW, with errors less than ±1.6°C from 20°C to 75°C.

A low power all-digital self-calibrated temperature sensor using 65nm FPGAs

This paper presents a thermal sensing and VLSI thermal management scheme using an array of on-chip all-digital delay-line based temperature sensors. A fully digital self-calibration method that removes the temperature sensors' sensitivities to supply voltage and process variations is proposed. The proposed calibration method assigns a unique correction factor, N
 C 
to each sensor, making all the sensors' calibrated outputs to be the same at start-up. The correction factor is updated when supply voltage variations are detected. Only one calibration block is required to calibrate multiple delay-line based temperature sensors sequentially. For each additional sensor, only additional registers for storing N
 C 
are required. The proposed self-calibrated temperature sensors are demonstrated on an Altera Cyclone IV FPGA based VLSI thermal management system. Runtime thermal profiles for four cores mapped on the Cyclone IV FPGA chip using a hybrid dynamic thermal management (DTM) method are obtained. The percentage of time that each core spent in a particular temperature range is plotted in a histogram. A comparison of different DTM techniques demonstrates that the proposed hybrid DTM reduces the amount of time that the MPSoC spent at higher temperatures and larger thermal gradients, by 10% and 21%, respectively. In addition, the proposed hybrid DTM offers a 10% improvement in the average processing rate (instructions per second) when compared with the conventional global DFS approach.

Delay-line temperature sensors and VLSI thermal management demonstrated on a 60nm FPGA

This paper presents a 4-bit windowed delay line ADC implemented in 65 nm CMOS technology for VLSI dynamic voltage scaling power management applications. Good linearity is achieved in the proposed power and area efficient ADC without the use of resistors for compensation. The circuit performance was analyzed theoretically and verified experimentally. The measured DNL is within ±0.25 LSB and INL ±0.15 LSB. It occupies an area of 0.009 mm2. With a sampling rate of 4 MHz, the ADC is measured to consume a power of 14 µW with ENOB of 4.1 and voltage sensing range from 0.87 V to 1.32 V.

A power and area efficient 65 nm CMOS delay line ADC for on-chip voltage sensing

This brief proposes a successive approximation register (SAR) analog-to-digital converter (ADC) whose readout speed is improved by 33%, through applying a digital error correction (DEC) method, compared to an alternative without using the DEC technique. The proposed addition-only DEC alleviates the ADC’s incomplete settling errors, hence improving conversion rate while maintaining accuracy. It is based on a binary bridged SAR architecture with 4 redundant capacitors and conversion cycles, which ensure the ADC’s linearity of 10 bit within a 5 bit accuracy’s settling time. The proposed SAR keeps the same straightforward timing diagram as that in a conventional SAR ADC, incurring no offset to the ADC. Measurement results of 15 columns of SAR ADCs, sampling at 5 MS/s on the same CMOS image sensor (CIS) chip, show integral nonlinearity (INL) around 3 LSB (1LSB = 1 mV), when sampling at 5 MHz, after a proposed swift digital background calibration that incurs no additional hardware complexity. The CIS array read out by the proposed column-level SAR ADCs is measured reasonable photoelectron transfer characteristics.

/pdf/a-10-bit-5-ms-s-column-sar-adc-with-digital-error-correction-3ct1qckk2s.pdf

A 10 Bit 5 MS/s Column SAR ADC With Digital Error Correction for CMOS Image Sensors

This brief proposes employing each of the classical 4 transistor (4T) pinned photodiode (PPD) CMOS image sensor (CIS) pixels, for both imaging and temperature measurement, intended for compensating the CISs’ dark current, and dark signal non-uniformity (DSNU). The proposed temperature sensors rely on the thermal behavior of MOSFETs working in subthreshold region, when biased with ratiometric currents sequentially. Without incurring any additional hardware or penalty to the CIS, they are measured to have thermal curvature errors less than ±0.3 °C and $3~\sigma $ process variations within ±1.3 °C, from 108 sensors on 4 chips, over a temperature range from −20 °C to 80 °C. Each of them consumes 576 nJ/conversion at a conversion rate of 62 samples/s, when quantized by 1st-order 14 bit delta–sigma ADCs and fabricated using $0.18~\mu \text{m}$ CIS technology. Experimental results show that they facilitate digital compensation for average dark current and DSNU by 78% and 20%, respectively.

/pdf/a-cmos-imager-pixel-based-temperature-sensor-for-dark-10r38iw98x.pdf

Shuang Xie

Papers

A low power all-digital self-calibrated temperature sensor using 65nm FPGAs

Delay-line temperature sensors and VLSI thermal management demonstrated on a 60nm FPGA

A power and area efficient 65 nm CMOS delay line ADC for on-chip voltage sensing

A 10 Bit 5 MS/s Column SAR ADC With Digital Error Correction for CMOS Image Sensors

A CMOS-Imager-Pixel-Based Temperature Sensor for Dark Current Compensation