Sina Sayyah Ensan

TL;DR: A single-ended low-power 7T SRAM cell in FinFET technology enhances read performance by isolating the storage node from the read path by disconnecting the feedback path of the cross-coupled inverters during the write operation.

TL;DR: This paper presents a robust and low-power single-ended robust 11T near-threshold SRAM cell in 10-nm FinFET technology that eliminates write disturbance and enhances write performance by disconnecting the path between cross-coupled inverters during the write operation.

TL;DR: In this article, the authors proposed a low-leakage and high-writable 8T SRAM cell based on FinFET technology. This cell reduces leakage current and consequently leakage power by dynamically adjusting the back gate of the stacked independent-gate Fin-FET devices and increases the write static noise margin of the proposed cell due to their role in reducing the strength of the pull-down network of the cross-coupled inverters.

TL;DR: This work proposes F P arithmetic (adder/subtractor and multiplier) using Resistive RAM (ReRAM) crossbar based IMC and proposes a novel shift circuitry to lower the shift overhead inherently present in the FP arithmetic.

TL;DR: This brief proposes ReLOPE, a fully RRAM crossbar-based IMC to solve PDEs using the Runge–Kutta numerical method with 97% accuracy, and expands the operating range of solution by exploiting shifters to shift input data and output data.