Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

/pdf/3-d-ics-a-novel-chip-design-for-improving-deep-submicrometer-6k9by1rs19.pdf

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, instruction window wakeup and selection logic, and operand bypassing are analyzed. Each is modeled and Spice simulated for feature sizes of 0.8µm, 0.35µm, and 0.18µm. Performance results and trends are expressed in terms of issue width and window size. Our analysis indicates that window wakeup and selection logic as well as operand bypass logic are likely to be the most critical in the future.A microarchitecture that simplifies wakeup and selection logic is proposed and discussed. This implementation puts chains of dependent instructions into queues, and issues instructions from multiple queues in parallel. Simulation shows little slowdown as compared with a completely flexible issue window when performance is measured in clock cycles. Furthermore, because only instructions at queue heads need to be awakened and selected, issue logic is simplified and the clock cycle is faster --- consequently overall performance is improved. By grouping dependent instructions together, the proposed microarchitecture will help minimize performance degradation due to slow bypasses in future wide-issue machines.

/pdf/complexity-effective-superscalar-processors-5gift5cchx.pdf

Complexity-effective superscalar processors

A review of recent MOSFET threshold voltage extraction methods

A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.

Characterization adn reduction of variation for integrated circuits

The progressively decreasing feature size of the circuit components has tremendously increased the need for the global surface planarization of the various thin film layers that constitute the integrated circuit (IC). Global planarization, being one of the major solutions to meet the demands of the industry, needs to be achieved following the most efficient polishing procedure. Chemical mechanical polishing (CMP) is the planarization method that has been selected by the semiconductor industry today. CMP, an ancient process used for glass polishing, was adopted first as a microelectronic fabrication process by IBM in the 80 s for SiO2 polishing. To achieve efficient planarization at miniaturized device dimensions, there is a need for a better understanding of the physics, chemistry and the complex interplay of tribo-mechanical phenomena occurring at the interface of the pad and wafer in presence of the fluid slurry medium. In spite of the fact that CMP research has grown by leaps and bounds, there are some teething problems associated with CMP process such as delamination, microscratches, dishing, erosion, corrosion, inefficient post-CMP clean, etc.; research on which is still developing. The fundamental understanding of the CMP is highly necessary to characterize, optimize and model the process. The CMP process is ready to make a positive impact on 30% of the US$ 135 billion global semiconductor market. This paper presents an overview of CMP process in general, the science and mechanism of polishing, different metal and dielectric CMP processes. The impact of consumables on the CMP process, post-CMP cleaning, modeling of different CMP processes as well as the future trends are also discussed.

Chemical mechanical planarization for microelectronics applications

Pattern-dependent effects are a key concern in chemical-mechanical polishing (CMP) processes. In oxide CMP, variation in the interlevel dielectric (ILD) thickness across each die and across the wafer can impact circuit performance and reduce yield. In this work, we present new test mask designs and associated measurement and analysis methods to efficiently characterize and model polishing behavior as a function of layout pattern factors-specifically area, pattern density, pitch, and perimeter/area effects. An important goal of this approach is rapid learning which requires rapid data collection. While the masks are applicable to a variety of CMP applications including back-end, shallow-trench, or damascene processes, in this study we focus on a typical interconnect oxide planarization process, and compare the pattern-dependent variation models for two different polishing pads. For the process and pads considered, we find that pattern density is a strongly dominant factor, while structure area, pitch, and perimeter/area (aspect ratio) play only a minor role.

/pdf/rapid-characterization-and-modeling-of-pattern-dependent-1gu1coxpom.pdf

Rapid characterization and modeling of pattern-dependent variation in chemical-mechanical polishing

Data processing methods and computer display systems for computer aided design and electrical performance prediction of multilevel on-chip and off-chip interconnects. The invention specifically relates to parameterized graphical display and computation tools for calculation and display of capacitance and other electrical characteristics of multilevel VLSI, PCB, and MCM interconnects. Four subsystems are integrated: (a) a batch-mode computation module that combines a 2-D/3-D finite difference numerical simulation and a fast interpolation algorithm; (b) an interactive design mode with performance browsing, goal-directed synthesis, and on-line performance evaluation; (c) an interactive SPICE subcircuit generator and simulator; and (d) a spreadsheet-style graphical user interface.

Computer-aided design methods and apparatus for multilevel interconnect technologies

A new, simple method to measure the V T of an enhancement-mode MOSFET has been developed based on the analytical model of the subthreshold current. V T is determined to be the gate voltage at which the I DS reaches the constant threshold current, and this method is accurate over a wide range of device dimensions, bias conditions, and operating temperatures.

A simple and accurate method to measure the threshold voltage of an enhancement-mode MOSFET

A statistical metrology framework is used to identify systematic and random sources of interconnect structure (ILD thickness) variation. Electrical and physical measurements, TCAD simulations, design of experiments, signal processing, and statistical analysis are integrated via statistical metrology to deconvolve ILD thickness variation into constituent variation sources. In this way, insight into planarization variation is enabled; for a representative CMP process we find that die-level neighborhood interactions are comparable to die-level feature-dependent effects, and within each die, die-level variation is greater than wafer-level variation. The characterization of variation sources via statistical metrology is critical for improved process control, interconnect simulation, and robust circuit design.

http://www.hpl.hp.com/techreports/95/HPL-95-126.pdf

Using a statistical metrology framework to identify systematic and random sources of die- and wafer-level ILD thickness variation in CMP processes

A method and system of determining circuit performance-related characteristics, particularly delay and crosstalk, of interconnects includes defining a number of process variables which exhibit Gaussian distributions with respect to geometrical variances. A table of statistically based worst-case values representative of capacitances and resistances associated with different selections of the process variables is generated. In the preferred embodiment, the statistically based worst-case values are 3-sigma values. Also generated is a table of capacitance derivatives with respect to interconnect geometries. When a particular interconnect layout having selected process parameters is designated, the tables of 3-sigma values and derivatives are accessed to generate a resistance-capacitance (RC) net representative of the interconnect layout. The resistance and capacitance are correlated for each RC net and are partially determined by a randomized selection of values for geometries of the interconnect layout. The randomized selection of geometrical values is within the Gaussian distributions. Three-sigma delay and 3-sigma crosstalk may then be determined for the interconnect layout.

Soo-Young Oh

Papers

Rapid characterization and modeling of pattern-dependent variation in chemical-mechanical polishing

Computer-aided design methods and apparatus for multilevel interconnect technologies

A simple and accurate method to measure the threshold voltage of an enhancement-mode MOSFET

Using a statistical metrology framework to identify systematic and random sources of die- and wafer-level ILD thickness variation in CMP processes

Method and system for determining statistically based worst-case on-chip interconnect delay and crosstalk