Showing papers in "IEEE Transactions on Electron Devices in 1982"

Electron and hole mobilities in silicon as a function of concentration and temperature

Abstract: An analytical expression has been derived for the electron and hole mobility in silicon based on both experimental data and modified Brooks-Herring theory of mobility. The resulting expression allows one to obtain electron and hole mobility as a function of concentration up to \sim 10^{20} cm-3in an extended and continuous temperature range (250-500 K) within ± 13 percent of the reported experimental values.

A graphical representation of the piezoresistance coefficients in silicon

Abstract: The longitudinal and transverse piezoresistance coefficients, Π(300 K), at room temperature are plotted as a function of the crystal directions for orientations in the

Intensity enhancement in textured optical sheets for solar cells

Abstract: We adopt a statistical mechanical approach toward the optics of textured and inhomogeneous optical sheets. As a general rule, the local light intensity in such a medium will tend to be 2 n^{2}(x) times greater than the externally incident light intensity, where n(x) is the local index of refraction in the sheet. This enhancement can contribute toward a 4 n^{2}(x) increase in the effective absorption of indirect-gap semiconductors like crystalline silicon.

Improving resolution in photolithography with a phase-shifting mask

Abstract: The phase-shifting mask consists of a normal transmission mask that has been coated with a transparent layer patterned to ensure that the optical phases of nearest apertures are opposite. Destructive interference between waves from adjacent apertures cancels some diffraction effects and increases the spatial resolution with which such patterns can be projected. A simple theory predicts a near doubling of resolution for illumination with partial incoherence σ < 0.3, and substantial improvements in resolution for σ < 0.7. Initial results obtained with a phase-shifting mask patterned with typical device structures by electron-beam lithography and exposed using a Mann 4800 10X tool reveals a 40-percent increase in usuable resolution with some structures printed at a resolution of 1000 lines/mm. Phase-shifting mask structures can be used to facilitate proximity printing with larger gaps between mask and wafer. Theory indicates that the increase in resolution is accompanied by a minimal decrease in depth of focus. Thus the phase-shifting mask may be the most desirable device for enhancing optical lithography resolution in the VLSI/VHSIC era.

Metal-(n) AlGaAs-GaAs two-dimensional electron gas FET

Abstract: Theoretical calculations have been developed for a two-dimensional electron gas FET (TEGFET) constituted by a AlGaAs (n)-GaAs (n-or p-) heterostructure in which the Schottky gate is deposited on the AlGaAs(n) top layer. The theory takes into account: i) the subband splitting in the two-dimensional electron gas (2-DEG); and ii) the existence of an undoped AlGaAs spacer layer which has been found to enhance the electron mobility. The sheet carrier concentration of the TEGFET has been calculated, and a simple analytical formula has been established for the charge control in large and small gate FET.

A batch-fabricated silicon capacitive pressure transducer with low temperature sensitivity

Abstract: A batch-fabricated solid-state capacitive pressure transducer has been developed using silicon integrated-circuit technology The fabricated devices exhibit a dynamic range of 350 mmHg and a pressure sensitivity of about 1100 ppm/mmHg The temperature coefficient of zero-pressure offset is about +50 ppm/°C (less than 005 mmHg/°C) and the temperature coefficient of pressure sensitivity over the -20 to +50°C temperature span is about +275 ppm/°C (less than 004 mmHg/°C) when the device is used with an open or vacuum-sealed reference cavity These temperature coefficients are substantially lower than those of previously reported monolithic devices and are low enough that expensive temperature trims can be eliminated for many applications

Advantages of thermal nitride and nitroxide gate films in VLSI process

Abstract: Thin gate SiO 2 films thinner than 200 A often deteriorate throughout developmental VLSI processes, including refractory metal or silicide gates and ion- or plasma-assisted processes. Thermal nitridation of such SiO 2 films improves the MOS characteristics by producing surface protective layers against impurity penetration and by producing good interfacial characteristics. This fact indicates that a thermally grown silicon nitride film on a silicon substrate is the most promising candidate for a very-thin gate insulator. Experimental data show significant benefits from the nitride film for future VLSI devices.

Effect of scaling of interconnections on the time delay of VLSI circuits

Abstract: Effect of scaling of dimensions, i.e., increase in chip size and decrease in minimum feature size, on the RC time delay associated with interconnections in VLSIC's has been investigated. Analytical expressions have been developed to relate this time delay to various elements of technology, i.e., interconnection material, minimum feature size, chip area, length of the interconnect, etc. Empirical expressions to predict the trends of the technological elements as a function of chronological time have been developed. Calculations of time delay for interconnections made of poly-Si, WSi 2 , W, and Al have been done and they indicate that as the chip area is increased and other device-related dimensions are decreased the interconnection time delay becomes significant compared to the device time delay and in extreme cases dominates the chip performance.

Modeling and measurement of minority-carrier lifetime versus doping in diffused layers of n + -p silicon diodes

Abstract: The results of minority-carrier lifetime measurements in heavily phosphorus-doped n+diffused layers of p-n junction diodes using a spectral response technique are reported in this paper. Exact modeling of current-flow equations, modified to include bandgap reduction due to high carrier concentration and Auger recombination, is used to compute the dependence of diffused-layer photocurrent J pth on the incident light energy and intensity. The photocurrent in the diffused layer is also obtained by subtracting the theoretical value of the space charge and uniformly doped p-region component from the experimentally measured photocurrent of the diode at each wavelength. Note that all calculated values based on light intensity include computed transmittance/reflectance through the oxide layer at each wavelength. The comparison of the values of J pth with J pexp , using nonlinear least square techniques, then directly gives the lifetime profile in the diffused layer. A simple expression is given for lifetime as a function of doping which may be used in modeling and prediction of device performance. Using this experimental technique it was found that the lifetime in the diffused layer is an order of magnitude less than that corresponding to uniformly doped bulk-silicon values and is very much process dependent; its value being 3.72 × 10-11s for surface concentration of 3.0 × 1020cm-3and increases to 2.9 × 10-8s at doping concentration of 1.0 × 1017cm-3.

Two-dimensional numerical simulation of energy transport effects in Si and GaAs MESFET's

Abstract: The results of computer simulations of submicron-scale Si and GaAs MESFET's which include carrier energy transport effects ("velocity overshoot") are presented. A new technique for solving the energy transport equation, which allows the description of short-time-scale carrier dynamics to be greatly improved without significantly increasing program complexity or computer time relative to conventional numerical simulations is described. The results indicate that the switching times of GaAs MESFET's should be less than would be predicted by conventional numerical models, and are consistent with experimental results.

The concept of generation and recombination lifetimes in semiconductors

Abstract: The purpose of this brief is to discuss the concept of generation and recombination lifetimes, a concept frequently confused in the literature. The regimes of device operation where they apply is discussed and it is shown experimentally for the first time that the two can be very different in magnitude.

A simple model for the overlap capacitance of a VLSI MOS device

Abstract: A simple approximate analytical expression for the overlap capacitance between gate- and source-drain of a VLSI MOS device is derived. The expression takes into account finite polysilicon gate thickness, source-drain junction depth and different dielectric constants of silicon and oxide. A numerical procedure is also described to calculate the exact overlap capacitance with fringing, using the solution of Laplace's equation. A comparison is made to check the accuracy of the analytical expression. Good agreement is found. Experimently obtained gate-source capacitance curves are described. Overlap capacitance and fringing component values derived from these curves are also in good agreement to those predicted by the model.

A high-sensitivity integrated-circuit capacitive pressure transducer

Abstract: A high-sensitivity capacitive pressure transducer with active processing circuit on the chip has been demonstrated and evaluated. The transducer configuration has been optimized by computer-aided design to achieve highest sensitivity for a given maximum dimension. The measured sensitivity of the devices is in the range of 50-150 µV/ V . mmHg, which is approximately one order of magnitude higher than the sensitivity of the piezoresistive pressure transducer of comparable size. Theoretical analysis also shows that a sensitivity on the order of 1000 µV/V . mmHg is also possible using the capacitive approach if the dimension of the device can be enlarged and the full scale pressure range is lowered. Other characteristics of the devices have been investigated and are presented.

Fabrication of high-performance LDDFET's with Oxide sidewall-spacer technology

Abstract: A fabrication process for the Lightly Doped Drain/Source Field-Effect Transistor, LDDFET, that utilizes RIE produced SiO 2 sidewall spacers is described. The process is compatible with most conventional polysilicon-gated FET processes and needs no additional photomasking steps. Excellent control and reproducibility of the n-region of the LDD device are obtained. Measurements from dynamic clock generators have shown that LDDFET's have as much as 1.9X performance advantage over conventional devices.

Ion-sensitive field-effect transistors with inorganic gate oxide for pH sensing

Abstract: Ion-sensitive field-effect transistors (ISFET's) have been fabricated by using silicon films on sapphire substrates (SOS) Using this structure SiO 2 , ZrO 2 , and Ta 2 O 5 films are examined as hydrogenion-sensitive materials, and Ta 2 O 5 film has been found to have the highest pH sensitivity (56 mV/pH) among them The measured pH sensitivity of this SOS-ISFET's is compared with the theoretical sensitivity based on the site-binding model of proton dissociation reaction on the metal oxide film and good agreement between them is obtained

An analytical breakdown model for short-channel MOSFET's

Abstract: Avalanche-induced breakdown mechanisms for short-channel MOSFET's are discussed. A simple analytical model that combines the effects due to the ohmic drop caused by the substrate current and the positive feedback effect of the substrate lateral bipolar transistor is proposed. It is shown that two conditions must be satisfied before breakdown will occur. One is the emission of minority carriers into the substrate from the source junction, the other is sufficient avalanche multiplication to cause significant positive feedback. Analytical theory has been developed with the use of a published model for short-channel MOSFET's. The calculated breakdown characteristics agree well with experiments for a wide range of processing parameters and geometries.

Submicrometer MOSFET structure for minimizing hot-carrier generation

Abstract: This paper reports on investigation of channel hot-carrier generation for various device structures. The dependences of channel hot-carrier generation on MOSFET structure are characterized by measuring the gate current and the substrate current as low as on the order of 10-15A. The measured gate current due to hot-electron injection into the oxide is modeled numerically as thermionic emission from heated electron gas over the Si-SiO 2 energy barrier. The substrate current due to hot-hole injection into the substrate is also modeled analytically. On the basis of the experiments and analyses, two device structures are proposed for minimizing hot-carrier generation and associated problems in submicrometer MOSFET: a graded drain junction structure and an offset gate structure. The proposed device structures provide remarkable improvements, raising by 2 V the highest applicable voltages as limited by hot-electron injection, as well as raising by 1-3 V the drain sustaining voltages as determined by the substrate hot-hole current. The influence of electron-beam radiation on the gate oxide is also discussed in relation to the trapping of hot electrons.

Backgating in GaAs MESFET's

Abstract: The phenomenon of backgating in GaAs depletion mode MESFET devices is investigated. The origin of this effect is electron trapping on the Cr2+and EL(2) levels at the semi-insulating substrate-channel region interface. A model describing backgating, based on DLTS and spectral measurements, is presented. Calculations based on this model predict that closely compensated substrate material will minimize backgating. Preliminary experimental data support this prediction.

A SEM-EBIC minority-carrier diffusion-length measurement technique

Abstract: A SEM-EBIC minority-carrier diffusion-length measurement technique is described, whereby an arrangement is used such that the electron beam is incident normal to the charge-collecting barrier; the barrier may be either that of a Schottky diode or of a shallow p-n junction. The beam is slowly moved away from the barrier and the diffusion length is found by analyzing the resulting EBIC decay. It is shown that in many practical cases this decay is given by I(d) \propto \exp (-d/L)/d^{3/2} where L is the diffusion length and d the beam-to-diode distance. Some experimental details concerning the application of the technique are discussed, and finally the technique is used to measure the diffusion length of a number of Si and GaP samples.

A batch-fabricated silicon thermopile infrared detector

Abstract: A thermopile infrared detector fabricated using silicon integrated-circuit technology is described. The device uses a series-connected array of thermocouples whose hot junctions are supported an a thin silicon membrane formed using anisotropic etching and a diffused boron etch stop. The membrane size and thickness control the speed and responsivity of the structure, which can be designed for a given application. For a 2-mm × 2-mm × 1-µm silicon membrane containing sixty bismuth-antimony couples, the structure produces a responsivity of 6 V/W and a time constant of about 15 ms. The use of polysilicon-gold couples can improve the responsivity to nearly 10 V/W while maintaining the same speed, simplifying the process, and retaining compatibility with on-chip signal processing circuitry.

Micromechanical accelerometer integrated with MOS detection circuitry

Abstract: A cantilever beam accelerometer is described in which the small cantilever sensing element is integrated with and fabricated alongside MOS detection circuitry. The total area of the detector/circuit combination is about 15000 µm2(24 mil2). Fully compatible and conventional materials and processing steps are employed throughout the fabrication schedule. Accelerations of the chip normal to its surface induce motions in the cantilever beam. These motions result in capacitance variations which drive the simple MOS detection circuit. Sensitivities of about 2.2 mV/g of acceleration were measured, corresponding to beam motions of about 68 nm/g, with a beam mechanical resonant frequency of 2.2 kHz. These results were in close agreement with detailed mechanical calculations and circuit modeling.

Integrated silicon microbeam PI-FET accelerometer

Abstract: Integrated accelerometers showing excellent linearity have been designed and fabricated using silicon planar technology, zinc-oxide sputtering, and anisotropic etching. Small cantilevered beam structures overcoated with piezoelectric ZnO films act as force transducers, and the electrical signal is directly coupled to the gate of a depletion-mode, p-channel MOS transistor. The accelerometers have a nearly flat response from very low frequencies until beam resonances become significant (above 40 kHz). The near-dc response results from completely isolating the piezoelectric film from electrical leakage paths. Measured performance has matched very well with theory. Theoretical analysis has been used to derive useful design tradeoffs.

A transmission line model for silicided diffusions: Impact on the performance of VLSI circuits

Abstract: In scaled technologies, performance improvements become increasingly limited by interconnect parasitics. The increased emphasis in the literature on low-resistance replacements for, or supplements to, polysilicon-gate technologies verifies the importance of parasitic limitations. Further, the role of the series source and drain resistance as well as contact resistance in limiting device performance has also been addressed by several authors. This role is further enhanced by the actual much more rapid increase in sheet resistivity with decreasing junction depth than previously assumed by other workers. In fact, it can be anticipated that metallurgical advances, such as silicides, will be required to compensate for the increased sheet resistance of source and drain diffusions. In the present work, a theoretical development of a transmission line model for a totally silicided diffusion is presented. Both the silicide and the diffusion sheet resistivities ρ S and ρ D , and the specific contact resistivity ρ c , are incorporated, unlike earlier models for contact holes only in which ρ S = 0. This model is applied to specific typical MOS structures, including single-section and three-section structures, to calculate the contact resistance contribution to total resistance. These results are used in conjunction with device equations addressing the device and circuit performance of small-geometry MOSFET's. Both n- and p-channel devices are considered as well as various scaling scenarios (constant field, constant voltage, etc.). These results show that for n-channel devices with a gate length of 1 µm, a-factor-of-two increase in circuit performance can be expected when using silicides. However, for p-channel devices, the expected performance gain as a result of using silicides is a factor of ten.

Distributed series resistance effects in solar cells

Abstract: A mathematical treatment is presented of the effects of one-dimensional distributed series resistance in solar cells. A general perturbation theory is developed, including consistently the induced spatial variation of diode current density and leading to a first-order equivalent lumped resistance of one third the total sheet resistance. For the case of diode characteristics of exponential type and distributed resistance of arbitrary size, unified numerical results are presented for both illuminated and dark characteristics. At high forward dark currents, the distributed series resistance is shown to cause an effective doubling of the "diode quality factor."

1/f noise in n-channel silicon-gate MOS transistors

Abstract: It is found that equivalent gate noise power for l/f noise in n-channel silicon-gate MOS transistors at near zero drain voltage at room temperature is empirically described by two noise terms, which vary as K_{1}(q/C_{ox}) (V_{G} -V_{T})/f and K_{2}(q/C_{ox})^{2}/f, where V_{G} is gate voltage, V T is threshold Voltage, and C ox is gate-oxide capacitance per unit area. Unification of carrier-density fluctuation (McWhorter's model)and mobility fluctuation (Hooge's model) can account for the experimental data. The comparison between the theory and experiment shows that the carrier fluctuation term K 2 is proportional to oxide-trap density at Fermi-level. The mobility fluctuation term K 1 is correlated to K 2 , being proportional to \radic K_{2} . The origin of this correlation is yet to be clarified.

A new method for experimental determination of the series resistance of a solar cell

Abstract: A new method for determining the series resistance of a solar cell from illuminated I-V measurements is presented. The method, based on the computation of the area A , under the I-V curve, evaluates R s using the equation R_{s} = 2[V_{oc}/I_{sc} - A/_sc^2 - (mkT/q) (1/I_{sc})] This technique takes advantage of the special feature of integration as a procedure to smooth data errors. The R s obtained represents the resistive effects globally.

A simple and accurate method to measure the threshold voltage of an enhancement-mode MOSFET

Abstract: A new, simple method to measure the V T of an enhancement-mode MOSFET has been developed based on the analytical model of the subthreshold current. V T is determined to be the gate voltage at which the I DS reaches the constant threshold current, and this method is accurate over a wide range of device dimensions, bias conditions, and operating temperatures.

Quadruply self-aligned stacked high-capacitance RAM using Ta 2 O 5 high-density VLSI dynamic memory

Abstract: A new one-transistor, one-capacitor RAM cell structure called a Quadruply Self-Aligned Stacked High Capacitance (QSA SHC) RAM is proposed as a basic cell for a future one-million-bit VLSI memory. This cell consists of a QSA MOSFET and a Ta 2 O 5 capacitor stacked on it. By this cell, the ultimate cell area 3F \times 2F can be realized with sufficient operating margin. Here, F is the minimum feature size. The basic cell was fabricated and its operation was experimentally verified. The leakage current of Ta 2 O 5 film was small enough for the storage capacitor dielectric. Using a 3F \times 4F cell and a 4F pitch sense amplifier, a one-million-bit memory was designed with a 2-µm rule. A cell size of 6.5 × 8 µm2, and a chip size of 9.2 × 9.5 mm2were obtained. The access time, neglecting the RC time constant of the word line, was estimated to be about 170 ns. Based on this design, it is argued that a future one-million-bit memory can be realized by QSA SHC technology with a 2-1-µm process. The mask set of the 1-Mbit RAM was actually fabricated by an electron-beam mask maker. A photomicrograph of the 1-Mbit RAM chip patterned by the mask set is shown. This chip was patterned not to get an operating sample but to show an actual chip image of the future 1- Mbit RAM. The area of each circuit block including storage array can be seen in this chip image.

SENSIM: A simulation program for solid-state pressure sensors

Abstract: A simulation program is described which is capable of calculating the output response of silicon piezoresistive or capacitive pressure sensors as a function of both pressure and temperature. A thermoelastic plane-stress formulation is used in calculating the stress and deflection of the transducer diaphragm. Both analytical and finite-difference solution methods are available, depending on the sensor structure. Diaphragm thickness taper, oxide and package stress, and rim effects are simulated. For capacitive structures, the program accurately predicts the diaphragm deflection and pressure sensitivity as a function of pressure and temperature. Stepped diaphragm structures are shown to be capable of improving pressure sensitivity by as much as 50 percent. The package-induced thermal drift for electrostatically sealed glass-silicon devices is typically less than 0.05 mmHg/°C.

A bird's beak free local oxidation technology feasible for VLSI circuits fabrication

Abstract: This paper presents a bird's beak free and fully recessed local oxidation-isolation structure employing only conventional LSI processing techniques; no additional masking step is required. A SideWAll Masked Isolation (SWAMI) process employing anisotropic plasma silicon etching and anisotropic plasma silicon nitride etching was implemented to form this new isolation structure. The SWAMI isolation scheme almost completely eliminates the reduction in effective channel width from drawn mask dimensions. The effective channel width obtained with the SWAMI isolation structure is independent of field-oxide thickness unlike the-conventional LOCOS process. Fabrication technology and device characteristics of MOSFET's fabricated with the SWAMI isolation structure will be compared with the conventional LOCOS isolated MOSFET's.