S
Sri Parameswaran
Researcher at University of New South Wales
Publications - 260
Citations - 3191
Sri Parameswaran is an academic researcher from University of New South Wales. The author has contributed to research in topics: Cache & Cache pollution. The author has an hindex of 28, co-authored 241 publications receiving 2761 citations. Previous affiliations of Sri Parameswaran include Tampere University of Technology & NICTA.
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Proceedings ArticleDOI
NoCGEN:a template based reuse methodology for Networks On Chip architecture
J. Chan,Sri Parameswaran +1 more
TL;DR: NoCGEN, a Network On Chip (NoC) generator, is described, which is used to create a simulatable and synthesizable NoC description, which was simulated with random traffic using a mixed SystemC/VHDL environment to ensure correctness of operation and to obtain performance and average latency.
Journal ArticleDOI
Processor Design for Soft Errors: Challenges and State of the Art
TL;DR: This article introduces the soft error problem from the perspective of processor design and provides a survey of the existing soft error mitigation methods across different levels of design abstraction involved in processor design, including the devicelevel, the circuit level, the architectural level, and the program level.
Proceedings ArticleDOI
RIJID: random code injection to mask power analysis based side channel attacks
TL;DR: A HW/SW based randomized instruction injection technique is proposed in this paper to overcome the pitfalls of previous countermeasures and injects random instructions at random places during the execution of an application which protects the system from both SPA and DPA.
Journal ArticleDOI
Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication
TL;DR: This paper proposes a novel error-configurable minimally biased approximate integer multiplier (MBM) design, and proposes an optimization of the MBM and a class of state-of-the-art approximate integer multipliers (DRUM and SSM) so that they can be efficiently used in approximate floating-point (FP) multipliers.
Proceedings ArticleDOI
Finding optimal L1 cache configuration for embedded systems
TL;DR: A method is given to rapidly find the L1 cache miss rate of an application and an energy model and an execution time model are developed to find the best cache configuration for the given embedded application.