There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The lion's share of bacteria in various environments cannot be cloned in the laboratory and thus cannot be sequenced using existing technologies. A major goal of single-cell genomics is to complement gene-centric metagenomic data with whole-genome assemblies of uncultivated organisms. Assembly of single-cell data is challenging because of highly non-uniform read coverage as well as elevated levels of sequencing errors and chimeric reads. We describe SPAdes, a new assembler for both single-cell and standard (multicell) assembly, and demonstrate that it improves on the recently released E+V-SC assembler (specialized for single-cell data) and on popular assemblers Velvet and SoapDeNovo (for multicell data). SPAdes generates single-cell assemblies, providing information about genomes of uncultivatable bacteria that vastly exceeds what may be obtained via traditional metagenomics studies. SPAdes is available online ( http://bioinf.spbau.ru/spades ). It is distributed as open source software.

SPAdes, a new genome assembly algorithm and its applications to single-cell sequencing ( 7th Annual SFAF Meeting, 2012)

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

To alleviate the complex communication problems that arise as the number of on-chip components increases, network-on-chip (NoC) architectures have been recently proposed to replace global interconnects. In this paper, we first provide a general description of NoC architectures and applications. Then, we enumerate several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation. Motivation, problem description, proposed approaches, and open issues are discussed for each problem from system, microarchitecture, and circuit perspectives. Finally, we address the interactions among these research problems and put the NoC design process into perspective.

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

Welcome to CODES'O2.This meeting marks the tenth anniversary of the forum that traces its roots to the first Hardware/Software Codesign Workshop held in Estes Park in fall 1992. A retrospective over a decade of the meeting reveals a strong and vibrant community of researchers that took the very first bold steps into uncharted territory. With researchers coming together from such diverse backgrounds as logic design, artificial intelligence and software engineering, the convergence was also as much marked by technical challenges as by the cultural understanding of what goes on the other side. The yin-and-yang of hardware and software gyrated around technical issues such as system modeling, system partitioning and synthesis. Through discussions the community cross pollination was especially remarkable, with software community coming to appreciate that "software synthesis" has little to do with erstwhile automatic program generation but optimization of software from formal models and specifications much the same way logic synthesis results in optimized logic netlists. That software can be optimized (against multiple competing criteria) much as hardware is routinely optimized by EDA tools was as much a revelation as the understanding that hardware/software codesign is really about systems engineering rather than application of a chain of automatic computer-aided design tools. Indeed, the discussions brought up similarities and lessons learnt in complex system designs from submarines to the Space Shuttle. This community was still shy of using the term "Embedded Systems," for in those days embedded systems often referred to microcontroller-based systems marked by low criticality, low performance and cost sensitive designs. Over a decade, however, as mainstream computing has increasingly become a part of our daily lives -- and indeed often incorporates components and technologies that are on the cutting edge of performance and functionality achievable today -- that reticence has been abandoned. Embedded systems, particularly those for microelectronic on-chip implementations, have come to characterize a major component of the meeting. CODES sessions in recent years have addressed issues such as architectural design, design space exploration and validation of such systems. Energy efficiency and performance modeling (including real-time performance) have become major research themes.We are happy to report that after ten active years of discussions, presentations and follow-ups, the CODES forum remains an active and vibrant community. We received a total of 76 papers out of which 25 papers were selected for full presentations and 11 papers for short presentations after a thorough review process that included, on an average, 4 to 5 reviews per paper. As always, the technical program at CODES is actively put together through discussions within the entire technical program committee of the symposium. It is a tribute to you -- the audience, authors and participants -- that the CODES keeps going strong. As we complete ten years of an active community participation, given the momentum and relevance of the technical challenges that we face in putting together complete systems (particularly for on-chip implementations) we are confident that CODES can look forward to many more years of technical contributions.

Proceedings of the tenth international symposium on Hardware/software codesign

The de-novo genome assembly is a challenging computational problem for which several pipelines have been developed. The advent of long-read sequencing technology has resulted in a new set of algorithmic approaches for the assembly process. In this work, we identify that one of these new and fast long-read assembly techniques (using Minimap2 and Miniasm ) can be modified for the short-read assembly process. This possibility motivated us to customize a long-read assembly approach for applications in a short-read assembly scenario. Here, we compare and contrast our proposed de-novo assembly pipeline ( MiniSR ) with three other recently developed programs for the assembly of bacterial and small eukaryotic genomes. We have documented two trade-offs: one between speed and accuracy and the other between contiguity and base-calling errors. Our proposed assembly pipeline shows a good balance in these trade-offs. The resulting pipeline is 6 and 2.2 times faster than the short-read assemblers Spades and SGA, respectively. MiniSR generates assemblies of superior N50 and NGA50 to SGA , although assemblies are less complete and accurate than those from Spades . A third tool, SOAPdenovo2 , is as fast as our proposed pipeline but had poorer assembly quality.

Fast Short Read De-Novo Assembly Using Overlap-Layout-Consensus Approach

Packet classification has become an important problem to solve in modern network processors used in networking embedded systems such as routers. Algorithms for matching incoming packets from the network to pre-defined rules, have been proposed by a number of researchers. Current software-based packet classification techniques have low performance, prompting many researchers to move their focus to new architectures encompassing both software and hardware components. Some of the newer hardware architectures exclusively utilize Ternary Content Addressable Memory (TCAM) to improve the performance of rule matching. However, this results in systems with high power consumption. TCAM consumes a high amount of power due to the fact that it reads the entire memory array during every access, much of which is unnecessary. In this paper, we propose LOP, a novel SRAM-based architecture where incoming packets are compared against parts of all rules simultaneously until a single matching rule is found for the compared bits in the packets. This method LOP significantly reduces power consumption as only a segment of the memory is compared against the incoming packet. Despite the additional time penalty to match a single packet, parallel comparison of multiple packets can improve throughput beyond that of the TCAMapproaches, while consuming significantly low power. Nine different benchmarks were tested in two classification systems, with results showing that LOP architectures provide high lookup rates and high throughput, and low power consumption. Compared with a state-of-the-art TCAM implementation (throughput of 495 Million Search per Second (Msps)) in 65nm CMOS technology, on average, LOP saves 43% of energy consumption with a throughput of 590Msps.

LOP: a novel SRAM-based architecture for low power and high throughput packet classification

Profiling in the ASP codesign environment

This article presents a method of modifying a processor so that it can estimate its own power and energy consumption in parallel with application execution. The authors have applied the method to an existing 32-bit processor and demonstrated it on a range of benchmarks. The system adds only a small increase in average power consumption and chip area.

Sri Parameswaran

Papers

Proceedings of the tenth international symposium on Hardware/software codesign

Fast Short Read De-Novo Assembly Using Overlap-Layout-Consensus Approach

LOP: a novel SRAM-based architecture for low power and high throughput packet classification

Profiling in the ASP codesign environment

Low-Impact Processor for Dynamic Runtime Power Management