There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The lion's share of bacteria in various environments cannot be cloned in the laboratory and thus cannot be sequenced using existing technologies. A major goal of single-cell genomics is to complement gene-centric metagenomic data with whole-genome assemblies of uncultivated organisms. Assembly of single-cell data is challenging because of highly non-uniform read coverage as well as elevated levels of sequencing errors and chimeric reads. We describe SPAdes, a new assembler for both single-cell and standard (multicell) assembly, and demonstrate that it improves on the recently released E+V-SC assembler (specialized for single-cell data) and on popular assemblers Velvet and SoapDeNovo (for multicell data). SPAdes generates single-cell assemblies, providing information about genomes of uncultivatable bacteria that vastly exceeds what may be obtained via traditional metagenomics studies. SPAdes is available online ( http://bioinf.spbau.ru/spades ). It is distributed as open source software.

SPAdes, a new genome assembly algorithm and its applications to single-cell sequencing ( 7th Annual SFAF Meeting, 2012)

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

To alleviate the complex communication problems that arise as the number of on-chip components increases, network-on-chip (NoC) architectures have been recently proposed to replace global interconnects. In this paper, we first provide a general description of NoC architectures and applications. Then, we enumerate several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation. Motivation, problem description, proposed approaches, and open issues are discussed for each problem from system, microarchitecture, and circuit perspectives. Finally, we address the interactions among these research problems and put the NoC design process into perspective.

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

Real-time encoding of video streams is computationally intensive and rarely carried out at high resolutions. In this paper, for the first time, we propose a platform for H.264 encoder which is both flexible (allows software upgrades) and scalable (supports multiple resolutions), and supports high video quality (by using both intraprediction and inter-prediction) and high throughput (by exploiting slice-level and pixel-level parallelisms). Our platform uses multiple Application Specific Instruction set Processors (ASIPs) with local and shared memories, and hardware accelerators (in the form of custom instructions). Our platform can be configured to use a particular number of ASIPs (slices per video frame) for a specific video resolution at design-time. The MPSoC architecture is automatically generated by our platform and the H.264 software does not need any modification, which enables quick design space exploration. We implemented the proposed platform in a commercial design environment, and illustrated its utility by creating systems with up to 170 ASIPs supporting resolutions up to HD1080. We further show how power gating can be used in our platform to save energy consumption.

Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs

Describes a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire delays of designs created by a high level synthesis system, and then finding an optimal clockwidth, we resynthesize the controller to improve performance without altering the datapath. Reclocking is versatile and can be applied not only for wire delay consideration, but also for bit-width migration, library migration and for feature size migration supporting the philosophy of design reuse. Experimental results show that with reclocking, the performance of the input designs can be improved by as much as 34%.

/pdf/reclocking-for-high-level-synthesis-d207yufdul.pdf

Reclocking for high-level synthesis

Cache memories have become an essential component in modern processors. To find the cache configuration that best fits the targeted power, timing and cost criteria of the system, designers conventionally run a lengthy cache simulation in software. In this paper we present MASH{fifo}, the first Multiple cAche Simulator in Hardware (MASH) supporting the FIFO replacement policy. We measured a speedup of up to 11x when compared to the fastest software alternative, CIPARSim. We also investigate an in-system implementation where multiple cache simulation is performed in real time from within an embedded system.

MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis

It is widely known that Multiprocessor Systems-on-Chip (MPSoC) is the driving force behind many embedded devices. State-of-the-art mobile phones and gaming consoles contain more than four processors in their MPSoC. Performance counters have become the recent trend in these devices to perform runtime adaptations to match power and performance budgets. In this paper, we propose a scalable performance monitoring unit (referred to as Event Monitoring Unit - EMU) for application specific MPSoC. Our monitors can be easily attached to an application specific processor as a hardware IP, to monitor any given event. The monitors are programmable, allowing customizable event handling and performance modeling for runtime adaptation and verification. Our programmable EMU costs very little hardware.

Scalable performance monitoring of application specific multiprocessor Systems-on-Chip

Computational needs for genome processing are often satiated by enormous servers or by cloud computers. Even though there has been some work in implementing some aspects of genome processing in GPUs and FPGAs, they are often accelerators for such servers and not stand-alone systems. In this paper, for the first time, we present a method to entirely move the alignment process to embedded processors. Such a system is useful in a variety of situations where significant networked infrastructure is not available, and where privacy is a concern. A ring pipelined processor architecture for short read alignment, based on partitioned genome references is shown. A timeout based alignment method is proposed to prevent unnecessary exhaustive search. The proposed partitioning method allows an entire human genome to be processed using small embedded processors. Experimental results show that the proposed solution speeds up the performance by approximately seven times with 16 embedded processors when compared to a linear pipelined system. It is expected that the proposed solution will to lead to a portable genome analyzing device, significantly reducing cost and testing time.

Sri Parameswaran

Papers

Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs

Reclocking for high-level synthesis

MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis

Scalable performance monitoring of application specific multiprocessor Systems-on-Chip

MESGA: an MPSoC based embedded system solution for short read genome alignment