An 11-bit, 50-MS/s time-to-digital converter (TDC) using a multipath gated ring oscillator with 6 ps of effective delay per stage demonstrates 1st-order noise shaping. At frequencies below 1 MHz, the TDC error integrates to 80 fs (rms) for a dynamic range of 95 dB with no calibration required. The 157 times 258 mum TDC is realized in 0.13 mum CMOS and, depending on the time difference between input edges, consumes 2.2 to 21 mA from a 1.5 V supply.

/pdf/a-multi-path-gated-ring-oscillator-tdc-with-first-order-1tcs8ib8qx.pdf

A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping

High-end mobile phones support multiple radio standards and a rich suite of applications, which involves advanced radio, audio, video, and graphics processing. The overall digital workload amounts to nearly 100GOPS, from 4b integer to 24b floating-point operations. With a power budget of only 1W this inevitably leads to heterogeneous multi-core architectures with aggressive power management. We review the state-of-the-art as well as trends.

Multi-core for mobile phones

A 12-bit Vernier ring time-to-digital converter (TDC) with time resolution of 8 ps for digital-phase-locked-loops (DPLL) is presented. This novel Vernier ring TDC places the Vernier delay cells and arbiters in a ring format and reuses them for the measurement of the input time interval. The proposed TDC thus achieves large detectable range, fine time resolution, small die size and low power consumption simultaneously. A pre-logic unit is developed to measure both positive and negative phase errors for DPLL applications. The TDC achieves a large detectable range of 12 bits with core area of 0.75 × 0.35 mm2 in a 0.13 μm CMOS technology. The total power consumption for the entire TDC chip is only 7.5 mW with a 1.5 V power supply, while operating at a clock frequency of 15 MSPS.

A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 $\mu{\hbox {m}}$ CMOS Technology

This paper presents a time-to-digital converter (TDC) architecture capable of reaching high-precision and high-linearity with moderate area occupation per measurement channel. The architecture is based on a coarse counter and a couple of two-stage interpolators that exploit the cyclic sliding scale technique in order to improve the conversion linearity. The interpolators are based on a new coarse-fine synchronization circuit and a new single-stage Vernier delay loop fine interpolation. In a standard cost-effective 0.35 μm CMOS technology the TDC reaches a dynamic range of 160 ns, 17.2 ps precision and differential non-linearity better than 0.9% LSB rms. The TDC building block was designed in order to be easily assembled in a multi-channel monolithic TDC chip. Coupled with a SPAD photodetector it is aimed for TCSPC applications (like FLIM, FCS, FRET) and direct ToF 3-D ranging.

A High-Linearity, 17 ps Precision Time-to-Digital Converter Based on a Single-Stage Vernier Delay Loop Fine Interpolation

A mm-wave digital transmitter based on a 60 GHz all-digital phase-locked loop (ADPLL) with wideband frequency modulation (FM) for FMCW radar applications is proposed. The fractional-N ADPLL employs a high-resolution 60 GHz digitally-controlled oscillator (DCO) and is capable of multi-rate two-point FM. It achieves a measured rms jitter of 590.2 fs, while the loop settles within 3 μs. The measured reference spur is only -74 dBc, the fractional spurs are below -62 dBc, with no other significant spurs. A closed-loop DCO gain linearization scheme realizes a GHz-level triangular chirp across multiple DCO tuning banks with a measured frequency error (i.e., nonlinearity) in the FMCW ramp of only 117 kHz rms for a 62 GHz carrier with 1.22 GHz bandwidth. The synthesizer is transformer-coupled to a 3-stage neutralized power amplifier (PA) that delivers +5 dBm to a 50 Ω load. Implemented in 65 nm CMOS, the transmitter prototype (including PA) consumes 89 mW from a 1.2 V supply.

https://researchrepository.ucd.ie/bitstream/10197/8627/1/2014-05_jssc_w-wu_mm-wave_tx_adpll.pdf

A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS

Time-to-digital converters (TDCs) are promising building blocks for the digitalization of mixed-signal functionality in ultra-deep-submicron CMOS technologies. A short survey on state-of-the-art TDCs is given. A high-resolution TDC with low latency and low dead-time is proposed, where a coarse time quantization derived from a differential inverter delay-line is locally interpolated with passive voltage dividers. This high-resolution TDC is monotonic by construction which makes the concept very robust against process variations. The feasibility is demonstrated by a 90 nm demonstrator which uses a 4x interpolation and provides a time domain resolution of 4.7 ps. An integral nonlinearity of 1.2 LSB and a differential nonlinearity of 0.6 LSB are achieved. The resolution restrictions imposed by an uncertainty of the stop signal and local variations are derived theoretically.

A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion

Time-to-digital converters (TDC) support the industry wide trend of replacing mixed-signal functionality by digital realizations. High-resolution TDCs become increasingly popular for time-of-flight measurements, full-speed testing, e.g., jitter measurement, clock and data recovery, measurement and instrumentation, and digital PLLs. As the speed leverage of technology scaling decreases below 100nm, robust TDCs with sub-gate-delay resolution are essential. The Vernier TDC requires long delay lines, thus suffers from large latency, area and power consumption. Latency and a resolution limited by the inherent variation-related pulse-width modification are the drawbacks of the pulse-shrinking approach. Parallel gradual-delay elements are particularly susceptible to process variations. The same holds for analog operations on time intervals like delay amplification. Ultra high-resolution TDCs achieve sub-ps resolution but require iterative conversion.

90nm 4.7ps-Resolution 0.7-LSB Single-Shot Precision and 19pJ-per-Shot Local Passive Interpolation Time-to-Digital Converter with On-Chip Characterization

A method is proposed to compensate for local delay variations by adjusting the supply voltage of individual circuit blocks. In-situ characterization of sub-blocks allows for voltage adjustment with minimum safety margin. Different strategies and circuit techniques for in-situ delay characterization of sub-blocks are described and compared. A dual VDD/power switch scheme is proposed for discrete voltage assignment to individual sub-blocks. Experimental results are presented for a test module based on an ARM9 core, fabricated in 130-nm CMOS. Yield improvement and power reduction capabilities are demonstrated by Monte Carlo simulations. For a typical setting, a reduction of 10% in power can be achieved with the proposed dual VDD/power switch concept. Using more than two supply voltages is shown to produce only small additional power savings at the price of high area overhead. The effect of the proposed scheme increases with increasing intra-die variability, which makes it suitable especially for future technologies.

In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations

A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.

Time delay circuit and time to digital converter

An integrated circuit, comprising a first data retention element configured to retain the data, the first data retention element having a first setup time, and a second data retention element configured to retain the data, the second data retention element having a second setup time, the second data retention element further having a data input. The second data retention element is connected in parallel with the first data retention element, and the second data retention element is configurable via the data input such that the second setup time is longer than the first setup time.

Stephan Henzler

Papers

A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion

90nm 4.7ps-Resolution 0.7-LSB Single-Shot Precision and 19pJ-per-Shot Local Passive Interpolation Time-to-Digital Converter with On-Chip Characterization

In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations

Time delay circuit and time to digital converter

Integrated Circuit and Method for Operating an Integrated Circuit