At present, flexible displays are an important focus of research1,2,3 Further development of large, flexible displays requires a cost-effective manufacturing process for the active-matrix backplane, which contains one transistor per pixel One way to further reduce costs is to integrate (part of) the display drive circuitry, such as row shift registers, directly on the display substrate Here, we demonstrate flexible active-matrix monochrome electrophoretic displays based on solution-processed organic transistors on 25-μm-thick polyimide substrates The displays can be bent to a radius of 1 cm without significant loss in performance Using the same process flow we prepared row shift registers With 1,888 transistors, these are the largest organic integrated circuits reported to date More importantly, the operating frequency of 5 kHz is sufficiently high to allow integration with the display operating at video speed This work therefore represents a major step towards 'system-on-plastic'

Flexible active-matrix displays and shift registers based on solution-processed organic transistors.

A radio frequency integrated circuit (RFIC) tag consisting of an 8 bit CPU, a 4 kB ROM, a 512B SRAM, and an RF circuit, which communicates using 915 MHz UHF RF signals, has been developed on both a flexible substrate and a glass substrate. Each of the RFIC tags employs a single DES and an anti-side channel attack routine in firmware for secured communication, and occupies an area of 10.5 mm in width and 8.9 mm in height. The RFIC tag on the flexible substrate is 145 mum thick and weighs 262 mg, and the RFIC tag on the glass substrate consumes 0.54 mW at a power supply voltage of 1.5 V and communicates with a maximum range of 43 cm at a power of 30 dBm. The high-performance poly-silicon TFT technology on flexible substrate and glass substrate of 0.8 mum design rule, and a gate plus one metal layer are used for fabrication. The RFIC tag realizes stable internal clock generation and distribution by a digital control clock generator and a two-phase nonoverlap clock scheme, respectively.

UHF RFCPUs on Flexible and Glass Substrates for Secure RFID Systems

FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.

/pdf/finfets-and-other-multi-gate-transistors-541arp307w.pdf

FinFETs and Other Multi-Gate Transistors

A formula is derived, which shows that the subthreshold swing of field-effect interband tunnel transistors is not limited to 60 mV/dec as in the MOSFET. This formula is consistent with two recent reports of interband tunnel transistors, which show lower than 60-mV/dec subthreshold swings and provides two simple design principles for configuring these transistors. One of these principles suggests placing the gate adjacent to the tunnel junction. Modeling of this configuration verifies that sub-60-mV/dec swing is possible.

Low-subthreshold-swing tunnel transistors

RFID tags based on organic transistors are described, discussing in detail the IC blocks used to build the logic and the radio. Tags energized and read out at 13.56 MHz, de facto standard frequency for item-level identification, have been tested and enabled for the first time multiple-object identification, using different 6-bit codes. A complete 64-bit transponder, the most complex organic RFID tag reported to date, operates at 125 kHz and employs 1938 transistors

/pdf/a-13-56-mhz-rfid-system-based-on-organic-transponders-ye6nlw47yo.pdf

A 13.56-MHz RFID System Based on Organic Transponders

This work presents tunneling field effect transistors (TFET) fabricated with 130nm and 90nm process flows. Good performance of the TFET is achieved. A novel mixed TFET/CMOS (TCMOS) logic family exhibits the advantages with respect to power consumption. For the first time experimental results are presented for a TCMOS ring-oscillator based on a p-channel MOSFET and n-channel TFET. The benefits of the TFET used in analog circuits are outlined.

The tunneling field effect transistor (TFET) as an add-on for ultra-low-voltage analog and digital processes

The efficiency of body biasing for leakage reduction and performance improvement in a 90-nm CMOS low-power technology with triple-well option is evaluated. Static measurements of single devices and dynamic measurements of ring oscillators and 32-b parallel prefix adders are presented. Whereas forward biasing still provides a significant performance improvement of up to 37% for low-leakage devices with 2.2-nm gate oxide thickness, the application of reverse biasing to reduce subthreshold leakage currents is inefficient due to additional leakage currents such as gate leakage and gate-induced drain leakage. Experimental results confirm that, in 90-nm CMOS circuits, the efficiency of body biasing strongly depends on the device type and operating temperature. Moreover, the impact of the zero-temperature coefficient point on static device and dynamic circuit performance is investigated.

Efficiency of body biasing in 90-nm CMOS for low-power digital circuits

Leakage currents in 120 nm CMOS technology are dependent on STI-induced stress (STIS), inverse narrow-width effect (INWE), and statistical threshold voltage variations. In this paper, we analyze the impact of these effects on the gate-width dependence of the device off-current density. A threshold voltage model is proposed to describe the observed off-current minimum. STIS dominates the device behavior for large gate widths while INWE determines the off-current for gate widths below 1 /spl mu/m. Statistical threshold voltage variations are relevant for minimum-sized devices.

Impact of STI-induced stress, inverse narrow width effect, and statistical V/sub TH/ variations on leakage currents in 120 nm CMOS

In a first embodiment, a multi-fin component arrangement has a plurality of multi-fin component partial arrangements. Each of the multi-fin component partial arrangements has a plurality of electronic components, which electronic components have a multi-fin structure. At least one multi-fin component partial arrangement has at least one dummy structure, which at least one dummy structure is formed between at least two of the electronic components formed in the at least one multi-fin component partial arrangement. The dummy structure is formed in such a way that electrical characteristics of the electronic components formed in the multi-fin component partial arrangements are adapted to one another.

Multi-Fin Component Arrangement and Method for Manufacturing a Multi-Fin Component Arrangement

The invention relates to an on-chip self calibrating delay monitoring circuitry A circuitry arrangement comprises: a launching flip-flop; a programmable delay line which is coupled to the launching flip-flop and comprises a configuration unit; a time-to-digital converter which is coupled to the programmable delay line and comprises at least one delay element coupled to a corresponding sampling flip-flop; and a feedback loop circuit coupled to the time-to-digital converter and to the configuration unit, wherein the feedback loop circuit is applicable for providing at least one input signal to the configuration unit according to at least one output signal of the corresponding sampling flip-flop of the time-to-digital converter

Christian Pacha

Papers

The tunneling field effect transistor (TFET) as an add-on for ultra-low-voltage analog and digital processes

Efficiency of body biasing in 90-nm CMOS for low-power digital circuits

Impact of STI-induced stress, inverse narrow width effect, and statistical V/sub TH/ variations on leakage currents in 120 nm CMOS

Multi-Fin Component Arrangement and Method for Manufacturing a Multi-Fin Component Arrangement

On-chip self calibrating delay monitoring circuitry