This article presents an overview of the essential aspects in the fabrication of silicon and some silicon/germanium nanostructures by metal-assisted chemical etching. First, the basic process and mechanism of metal-assisted chemical etching is introduced. Then, the various influences of the noble metal, the etchant, temperature, illumination, and intrinsic properties of the silicon substrate (e.g., orientation, doping type, doping level) are presented. The anisotropic and the isotropic etching behaviors of silicon under various conditions are presented. Template-based metal-assisted chemical etching methods are introduced, including templates based on nanosphere lithography, anodic aluminum oxide masks, interference lithography, and block-copolymer masks. The metal-assisted chemical etching of other semiconductors is also introduced. A brief introduction to the application of Si nanostructures obtained by metal-assisted chemical etching is given, demonstrating the promising potential applications of metal-assisted chemical etching. Finally, some open questions in the understanding of metal-assisted chemical etching are compiled.

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Metal-Assisted Chemical Etching of Silicon: A Review

Porous anodic aluminum oxide: anodization and templated synthesis of functional nanostructures.

Silicon has long been established as the material of choice for the microelectronics industry. This is not yet true in photonics, where the limited degrees of freedom in material design combined with the indirect bandgap are a major constraint. Recent developments, especially those enabled by nanoscale engineering of the electronic and photonic properties, are starting to change the picture, and some silicon nanostructures now approach or even exceed the performance of equivalent direct-bandgap materials. Focusing on two application areas, namely communications and photovoltaics, we review recent progress in silicon nanocrystals, nanowires and photonic crystals as key examples of functional nanostructures. We assess the state of the art in each field and highlight the challenges that need to be overcome to make silicon a truly high-performing photonic material.

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Silicon nanostructures for photonics and photovoltaics

This paper summarizes some of the essential aspects of silicon-nanowire growth and of their electrical properties. In the first part, a brief description of the different growth techniques is given, though the general focus of this work is on chemical vapor deposition of silicon nanowires. The advantages and disadvantages of the different catalyst materials for silicon-wire growth are discussed at length. Thereafter, in the second part, three thermodynamic aspects of silicon-wire growth via the vapor–liquid–solid mechanism are presented and discussed. These are the expansion of the base of epitaxially grown Si wires, a stability criterion regarding the surface tension of the catalyst droplet, and the consequences of the Gibbs–Thomson effect for the silicon wire growth velocity. The third part is dedicated to the electrical properties of silicon nanowires. First, different silicon nanowire doping techniques are discussed. Attention is then focused on the diameter dependence of dopant ionization and the influence of interface trap states on the charge carrier density in silicon nanowires. It is concluded by a section on charge carrier mobility and mobility measurements.

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Silicon Nanowires: A Review on Aspects of their Growth and their Electrical Properties

The nanowire geometry provides potential advantages over planar waferbased or thin-film solar cells in every step of the photoconversion process. These advantages include reduced reflection, extreme light trapping, improved band gap tuning, facile strain relaxation, and increased defect tolerance. These benefits are not expected to increase the maximum efficiency above standard limits; instead, they reduce the quantity and quality of material necessary to approach those limits, allowing for substantial cost reductions. Additionally, nanowires provide opportunities to fabricate complex single-crystalline semiconductor devices directly on low-cost substrates and electrodes such as aluminum foil, stainless steel, and conductive glass, addressing another major cost in current photovoltaic technology. This review describes nanowire solar cell synthesis and fabrication, important characterization techniques unique to nanowire systems, and advantages of the nanowire geometry.

Nanowire Solar Cells

Large-area high density silicon nanowire (SiNW) arrays were fabricated by metal-assisted chemical etching of silicon, utilizing anodic aluminum oxide (AAO) as a patterning mask of a thin metallic film on a Si (100) substrate. Both the diameter of the pores in the AAO mask and the thickness of the metal film affected the diameter of SiNWs. The diameter of the SiNWs decreased with an increase of thickness of the metal film. Large-area SiNWs with average diameters of 20 nm down to 8 nm and wire densities as high as 10 10 wires/cm 2 were accomplished. These SiNWs were single crystalline and vertically aligned to the (100) substrate. It was revealed by transmission electron microscopy that the SiNWs were of high crystalline quality and showed a smooth surface.

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Extended arrays of vertically aligned sub-10 nm diameter [100] Si nanowires by metal-assisted chemical etching.

The metal-assisted etching direction of Si(110) substrates was found to be dependent upon the morphology of the deposited metal catalyst. The etching direction of a Si(110) substrate was found to be one of the two crystallographically preferred 100 directions in the case of isolated metal particles or a small area metal mesh with nanoholes. In contrast, the etching proceeded in the vertical [110] direction, when the lateral size of the catalytic metal mesh was sufficiently large. Therefore, the direction of etching and the resulting nanostructures obtained by metal-assisted etching can be easily controlled by an appropriate choice of the morphology of the deposited metal catalyst. On the basis of this finding, a generic method was developed for the fabrication of wafer-scale vertically aligned arrays of epitaxial [110] Si nanowires on a Si(110) substrate. The method utilized a thin metal film with an extended array of pores as an etching catalyst based on an ultrathin porous anodic alumina mask, while a prepatterning of the substrate prior to the metal depostion is not necessary. The diameter of Si nanowires can be easily controlled by a combination of the pore diameter of the porous alumina film and varying the thickness of the deposited metal film.

http://www.uripore.com/dat/NL9_2519_2009.pdf

Ordered arrays of vertically aligned [110] silicon nanowires by suppressing the crystallographically preferred etching directions.

A structure containing a ferroelectric material comprises a substrate such as silicon, a buffer layer formed on the substrate, and a non-c-axis-oriented, electrically-conductive template layer formed on the buffer layer. The template layer comprises a perovskite oxide compound. An epitaxially a-axis-oriented ferroelectric layer is formed on the template layer, and has a vector of spontaneous polarization oriented perpendicular or at least substantially perpendicular to the film normal.

Non-c-axis oriented bismuth-layered perovskite ferroelectric structure epitaxially grown on buffered silicon

A thermoelectric apparatus comprises at least one pair of adjacent portions of p-type and n-type semiconductor material each portion having respective, generally oppositely disposed, first and second surface regions. Said first surface regions of each said pair are coupled either directly, or indirectly via a metallic conductor, or indirectly via a doped electrically conductive semiconductor and said second surface regions are electrically connectable to an external circuit. The p-type and n-type semiconductor material comprises porous semiconductor material which allows a high dimensionless figure of merit to be achieved for either thermo-electrical power generation or thermo electrical cooling.

Stephan Senz

Papers

Extended arrays of vertically aligned sub-10 nm diameter [100] Si nanowires by metal-assisted chemical etching.

Ordered arrays of vertically aligned [110] silicon nanowires by suppressing the crystallographically preferred etching directions.

Non-c-axis oriented bismuth-layered perovskite ferroelectric structure epitaxially grown on buffered silicon

Thermoelectric apparatus and methods of manufacturing the same