This article presents an overview of the essential aspects in the fabrication of silicon and some silicon/germanium nanostructures by metal-assisted chemical etching. First, the basic process and mechanism of metal-assisted chemical etching is introduced. Then, the various influences of the noble metal, the etchant, temperature, illumination, and intrinsic properties of the silicon substrate (e.g., orientation, doping type, doping level) are presented. The anisotropic and the isotropic etching behaviors of silicon under various conditions are presented. Template-based metal-assisted chemical etching methods are introduced, including templates based on nanosphere lithography, anodic aluminum oxide masks, interference lithography, and block-copolymer masks. The metal-assisted chemical etching of other semiconductors is also introduced. A brief introduction to the application of Si nanostructures obtained by metal-assisted chemical etching is given, demonstrating the promising potential applications of metal-assisted chemical etching. Finally, some open questions in the understanding of metal-assisted chemical etching are compiled.

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Metal-Assisted Chemical Etching of Silicon: A Review

There are growing concerns over the environmental, climate, and health impacts caused by using non-renewable fossil fuels. The utilization of green energy, including solar and wind power, is believed to be one of the most promising alternatives to support more sustainable economic growth. In this regard, lithium-ion batteries (LIBs) can play a critically important role. To further increase the energy and power densities of LIBs, silicon anodes have been intensively explored due to their high capacity, low operation potential, environmental friendliness, and high abundance. The main challenges for the practical implementation of silicon anodes, however, are the huge volume variation during lithiation and delithiation processes and the unstable solid-electrolyte interphase (SEI) films. Recently, significant breakthroughs have been achieved utilizing advanced nanotechnologies in terms of increasing cycle life and enhancing charging rate performance due partially to the excellent mechanical properties of nanomaterials, high surface area, and fast lithium and electron transportation. Here, the most recent advance in the applications of 0D (nanoparticles), 1D (nanowires and nanotubes), and 2D (thin film) silicon nanomaterials in LIBs are summarized. The synthetic routes and electrochemical performance of these Si nanomaterials, and the underlying reaction mechanisms are systematically described.

Silicon-based Nanomaterials for Lithium-Ion Batteries - A Review

Porous anodic aluminum oxide: anodization and templated synthesis of functional nanostructures.

Silicon has long been established as the material of choice for the microelectronics industry. This is not yet true in photonics, where the limited degrees of freedom in material design combined with the indirect bandgap are a major constraint. Recent developments, especially those enabled by nanoscale engineering of the electronic and photonic properties, are starting to change the picture, and some silicon nanostructures now approach or even exceed the performance of equivalent direct-bandgap materials. Focusing on two application areas, namely communications and photovoltaics, we review recent progress in silicon nanocrystals, nanowires and photonic crystals as key examples of functional nanostructures. We assess the state of the art in each field and highlight the challenges that need to be overcome to make silicon a truly high-performing photonic material.

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Silicon nanostructures for photonics and photovoltaics

This paper summarizes some of the essential aspects of silicon-nanowire growth and of their electrical properties. In the first part, a brief description of the different growth techniques is given, though the general focus of this work is on chemical vapor deposition of silicon nanowires. The advantages and disadvantages of the different catalyst materials for silicon-wire growth are discussed at length. Thereafter, in the second part, three thermodynamic aspects of silicon-wire growth via the vapor–liquid–solid mechanism are presented and discussed. These are the expansion of the base of epitaxially grown Si wires, a stability criterion regarding the surface tension of the catalyst droplet, and the consequences of the Gibbs–Thomson effect for the silicon wire growth velocity. The third part is dedicated to the electrical properties of silicon nanowires. First, different silicon nanowire doping techniques are discussed. Attention is then focused on the diameter dependence of dopant ionization and the influence of interface trap states on the charge carrier density in silicon nanowires. It is concluded by a section on charge carrier mobility and mobility measurements.

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Silicon Nanowires: A Review on Aspects of their Growth and their Electrical Properties

Large-area high density silicon nanowire (SiNW) arrays were fabricated by metal-assisted chemical etching of silicon, utilizing anodic aluminum oxide (AAO) as a patterning mask of a thin metallic film on a Si (100) substrate. Both the diameter of the pores in the AAO mask and the thickness of the metal film affected the diameter of SiNWs. The diameter of the SiNWs decreased with an increase of thickness of the metal film. Large-area SiNWs with average diameters of 20 nm down to 8 nm and wire densities as high as 10 10 wires/cm 2 were accomplished. These SiNWs were single crystalline and vertically aligned to the (100) substrate. It was revealed by transmission electron microscopy that the SiNWs were of high crystalline quality and showed a smooth surface.

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Extended arrays of vertically aligned sub-10 nm diameter [100] Si nanowires by metal-assisted chemical etching.

An effective and low-cost method to fabricate hexagonally patterned, vertically aligned Si/Ge superlattice nanowires with diameters below 20 nm is presented. By combining the growth of Si/Ge superlattices by molecular beam epitaxy, prepatterning the substrate by anodic aluminum oxide masks, and finally metal-assisted chemical wet etching, this method generates highly ordered hexagonally patterned nanowires. This technique allows the fabrication of nanowires with a high area density of 10 10 wires/cm 2 , including the control of their diameter and length.

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Sub-20 nm Si/Ge superlattice nanowires by metal-assisted etching.

The semiconductor wafer has a substrate (1) having a substrate material. The layer structure (2) stands under a course or a compression stress and another layer structure compensates tension with compression stress or tensile stress. The substrate material is silicon. The latter layer structure contains a layer, which has a silicon oxide, a silicon oxynitride or a silicon nitride standing under compression stress. The former layer structure has a silicon germanium layer standing under tensile stress. The former layer structure has a gallium arsenide layer standing under tensile stress. An independent claim is also included for a method for producing a semiconductor wafer.

Semiconductor wafer for use as donor wafer, has layer structure that stands under course or compression stress and another layer structure compensates tension with compression stress or tensile stress

Manfred Dr. Reiche

Papers

Extended arrays of vertically aligned sub-10 nm diameter [100] Si nanowires by metal-assisted chemical etching.

Sub-20 nm Si/Ge superlattice nanowires by metal-assisted etching.

Semiconductor wafer for use as donor wafer, has layer structure that stands under course or compression stress and another layer structure compensates tension with compression stress or tensile stress