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Steven G. Walker
Researcher at IBM
Publications - 7
Citations - 1284
Steven G. Walker is an academic researcher from IBM. The author has contributed to research in topics: Equivalent circuit & Partial element equivalent circuit. The author has an hindex of 6, co-authored 7 publications receiving 1266 citations.
Papers
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Proceedings ArticleDOI
First-order incremental block-based statistical timing analysis
TL;DR: In this article, a canonical first order delay model is proposed to propagate timing quantities like arrival times and required arrival times through the timing graph in this canonical form and the sensitivities of all timing quantities to each of the sources of variation are available.
Journal ArticleDOI
First-Order Incremental Block-Based Statistical Timing Analysis
Chandu Visweswariah,Kaushik Ravindran,Kerim Kalafala,Steven G. Walker,Sambasivan Narayan,D.K. Beece,Jeffrey S. Piaget,Natesan Venkateswaran,Jeffrey G. Hemmett +8 more
TL;DR: A canonical first-order delay model that takes into account both correlated and independent randomness is proposed, and the first incremental statistical timer in the literature is reported, suitable for use in the inner loop of physical synthesis or other optimization programs.
Journal ArticleDOI
Full-wave PEEC time-domain method for the modeling of on-chip interconnects
TL;DR: It is shown that a full-wave partial element equivalent circuit method, which includes the delays among the partial elements, leads to an efficient solver enabling the analysis of large meaningful problems for realistic very large scale integration wiring problems.
Proceedings ArticleDOI
Dealing with inductance in high-speed chip design
TL;DR: This tutorial will attempt to demystify on- chip inductance through the discussion of several illustrative on-chip examples analyzed using full-wave extraction and simulation methods.
Patent
System and method for derivative-free optimization of electrical circuits
TL;DR: In this paper, the authors present a system and method for optimizing electrical circuits by means of derivative-free optimization, where any method of measuring the performance of the circuit, including computer simulation, can be incorporated into the optimization technique, with no derivative requirements.