Sudarshan Banerjee

TL;DR: A physically aware hardware-software (HW-SW) scheme for minimizing application execution time under HW resource constraints, where the HW is a reconfigurable architecture with partial dynamic reconfiguration capability.

TL;DR: This work presents an exact approach for hardware-software (HW-SW) partitioning that guarantees correctness of implementation by considering placement implications as an integral aspect of HW-SW partitioning and presents a physically aware HW- SW partitioning heuristic that simultaneously partitions, schedules, and does linear placement of tasks on such devices.

TL;DR: This work presents ISEGEN, an approach that identifies high-quality ISEs by iterative improvement following the basic principles of the well-known Kernighan-Lin (K-L) min-cut heuristic, and shows that the ISEs identified by the technique exhibit 35% more speedup than the genetic solution on a large cryptographic applications by effectively exploiting its regular structure.

TL;DR: In this paper, an approach that identifies high-quality ISEs by iterative improvement following the basic principles of the well-known Kernighan-Lin (K-L) min-cut heuristic is presented.

TL;DR: In this paper, the authors proposed a new cost function for SA that allows frequent discovery of better partitioning solutions by searching spaces overlooked by traditional SA cost functions, and showed that the SA cost function can be used to locate better design points with over 10% improvement in application execution time compared to the solutions generated by a Kernighan-Lin partitioning algorithm starting with an all-SW partitioning.