S
Suk-Chon Kwon
Researcher at Samsung
Publications - 6
Citations - 794
Suk-Chon Kwon is an academic researcher from Samsung. The author has contributed to research in topics: EPROM & Flash memory. The author has an hindex of 4, co-authored 4 publications receiving 744 citations.
Papers
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Journal ArticleDOI
A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme
Kang-Deog Suh,Byung-Hoon Suh,Young-Ho Lim,Jin-Ki Kim,Young-joon Choi,Yong-Nam Koh,Sung-Soo Lee,Suk-Chon Kwon,Byung-Soon Choi,Jin-Sun Yum,Jung-Hyuk Choi,Jang-Rae Kim,Hyung-Kyu Lim +12 more
TL;DR: A 3.3 V-only 32 Mb NAND flash memory that achieves not only high performance but also low cost with a 94.9 mm/sup 2/ die size, improved yields, and a simple process with 0.5 /spl mu/m CMOS technology is described.
Journal ArticleDOI
A 120-mm/sup 2/ 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed
Jin-Ki Kim,Koji Sakui,Sung-Soo Lee,Y. Itoh,Suk-Chon Kwon,Kazuhisa Kanazawa,Kijun Lee,Hiroshi Nakamura,Kang-Young Kim,Toshihiko Himeno,Jang-Rae Kim,Kazushige Kanda,Tae-Sung Jung,Y. Oshima,Kang-Deog Suh,Kazuhiko Hashimoto,Sung-Tae Ahn,Junichi Miyamoto +17 more
TL;DR: A 64 Mb NAND flash memory having improved read and program performances is described, by improving the page sensing time and employing the full-chip burst read capability.
Journal Article
A 120mm^2 64Mb NAND Flash Memory Achieving 180ns/byte Effective Program Speed
Kazuhisa Kanazawa,Jin-Ki Kim,Koji Sakui,Sung-Soo Lee,Yasuo Itoh,Suk-Chon Kwon,Hiroshi Nakamura,Kijun Lee,Toshihiko Himeno,Kang-Young Kim,Kazushige Kanda,Jang-Rae Kim,Yoichi Oshima,Tae-Sung Jung,Kazuhiko Hashimoto,Kang-Deog Suh,Junichi Miyamoto,Sung-Tae Ahn +17 more
Proceedings ArticleDOI
A 120 mm/sup 2/ 64 Mb NAND flash memory achieving 180 ns/byte effective program speed
Jin-Ki Kim,Koji Sakui,Sung-Soo Lee,J. Itoh,Suk-Chon Kwon,Kazuhisa Kanazawa,Ji-Jun Lee,Hiroshi Nakamura,Kang-Young Kim,Toshihiko Himeno,Jang-Rae Kim,Kazushige Kanda,Tae-Sung Jung,Y. Oshima,Kang-Deog Suh,Kazuhiko Hashimoto,Junichi Miyamoto +16 more
TL;DR: This paper describes a 3.3 V-only 64 Mb NAND flash memory fabricated using a 0.4 /spl mu/m single-metal CMOS technology that achieves a read throughput of 40 MB/s and a program throughput of 5MB/s using a narrow incremental step pulse programming (NISPP) technique.
Proceedings ArticleDOI
A Multi-Mode 8K-MAC HW-Utilization-Aware Neural Processing Unit with a Unified Multi-Precision Datapath in 4nm Flagship Mobile SoC
Jun-Seok Park,Changsoo Park,Suk-Chon Kwon,Hyeong Seok Kim,Tae Keun Jeon,Yesung Kang,Heonsoo Lee,Dongwoo Lee,James Kim,Youngjik Lee,Sangkyu Park,Jun Woo Jang,Sanghyuck Ha,MinSeong Kim,Jihoon Bang,Suk Hwan Lim,In-Kwon Kang +16 more
TL;DR: A neural processing unit (NPU) optimized with reconfigurable data prefetching and operational flow for high compute utilization, and a dynamic operation mode to cover extremely low-power or low-latency requirements that provides the flexibility needed by real world applications within the power constraints of various product domains is presented.