With the explosive growth of digital data in the era of the Internet of Things (IoT), fast and scalable memory technologies are being researched for data storage and data-driven computation. Among the emerging memories, resistive switching memory (RRAM) raises strong interest due to its high speed, high density as a result of its simple two-terminal structure, and low cost of fabrication. The scaling projection of RRAM, however, requires a detailed understanding of switching mechanisms and there are potential reliability concerns regarding small device sizes. This work provides an overview of the current understanding of bipolar-switching RRAM operation, reliability and scaling. After reviewing the phenomenological and microscopic descriptions of the switching processes, the stability of the low- and high-resistance states will be discussed in terms of conductance fluctuations and evolution in 1D filaments containing only a few atoms. The scaling potential of RRAM will finally be addressed by reviewing the recent breakthroughs in multilevel operation and 3D architecture, making RRAM a strong competitor among future high-density memory solutions.

https://iopscience.iop.org/article/10.1088/0268-1242/31/6/063002/pdf

Resistive switching memories based on metal oxides: mechanisms, reliability and scaling

Introduced the concept of floating-gate interference in flash memory cells for the first time The floating-gate interference causes V/sub T/ shift of a cell proportional to the V/sub T/ change of the adjacent cells It results from capacitive coupling via parasitic capacitors around the floating gate The coupling ratio defined in the previous works should be modified to include the floating-gate interference In a 012-/spl mu/m design-rule NAND flash cell, the floating-gate interference corresponds to about 02 V shift in multilevel cell operation Furthermore, the adjacent word-line voltages affect the programming speed via parasitic capacitors

Effects of floating-gate interference on NAND flash memory cell operation

A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

As NAND flash memory manufacturers scale down to smaller process technology nodes and store more bits per cell, reliability and endurance of flash memory reduce. Wear-leveling and error correction coding can improve both reliability and endurance, but finding effective algorithms requires a strong understanding of flash memory error patterns. To enable such understanding, we have designed and implemented a framework for fast and accurate characterization of flash memory throughout its lifetime. This paper examines the complex flash errors that occur at 30-40nm flash technologies. We demonstrate distinct error patterns, such as cycle-dependency, location-dependency and value-dependency, for various types of flash operations. We analyze the discovered error patterns and explain why they exist from a circuit and device standpoint. Our hope is that the understanding developed from this characterization serves as a building block for new error tolerance algorithms for flash memory.

/pdf/error-patterns-in-mlc-nand-flash-memory-measurement-598fgyt3mx.pdf

Error patterns in MLC NAND flash memory: measurement, characterization, and analysis

NAND flash memories have bit errors that are corrected by error-correction codes (ECC). We present raw error data from multi-level-cell devices from four manufacturers, identify the root-cause mechanisms, and estimate the resulting uncorrectable bit error rates (UBER). Write, retention, and read-disturb errors all contribute. Accurately estimating the UBER requires care in characterization to include all write errors, which are highly erratic, and guardbanding for variation in raw bit error rate. NAND UBER values can be much better than 10-15, but UBER is a strong function of program/erase cycling and subsequent retention time, so UBER specifications must be coupled with maximum specifications for these quantities.

Bit error rate in NAND Flash memories

While the performance of flash memory exceeds hard disk drives in almost every category, the cost of flash memory must come down in order to gain wider acceptance in mass storage applications. This paper describes a 3.3 V-only 32 Mb NAND flash memory that achieves not only high performance but also low cost with a 94.9 mm/sup 2/ die size, improved yields, and a simple process with 0.5 /spl mu/m CMOS technology. Die size is reduced by eliminating high voltage operation on the bitlines through a self boosted program inhibit voltage generation scheme. Incremental-step-pulse programming results in a 2.3 MB/s program data rate as well as improved process variation tolerance. Interleaved data paths and a boosted wordline results in a 25 ns burst cycle time and a 24 MB/s read data rate. Maximum operating current is less than 8 mA.

A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme

A nonvolatile semiconductor memory device particularly relates to an EEPROM having NAND-structured cells, and an optimizing programming method thereof. The device includes a memory cell array arranged as matrix having NAND cells formed by a plurality of serially-connected memory cells each of which is formed by stacking a charge storage layer and a control gate on a semiconductor substrate, and enables electrical erasing by the mutual exchange of a charge between the charge storage layer and the substrate, a data latch circuit, a high voltage supply circuit, a current source circuit, a program checking circuit, and a program status detecting circuit. The programming state is optimized while being unaffected by the variance of process parameters, over-programming is prevented by the use of a verifying potential, and the performance of the chip is enhanced by automatically optimizing the programming with a chip's internal verification function. External control is not required, which enhances performance of the overall system. Also, a page buffer of an existing flash memory having the page mode function is employed, which is applicable to the currently used products.

Nonvolatile semiconductor memory device and an optimizing programming method thereof

We present this letter on the combining effect of tunnel-oxide degradation and narrow width effect on the data retention characteristics of NAND flash memory cells. Due to severe boron segregation in shallow-trench isolation (STI) corner, the cell transistor suffers from intense VTH shift on STI corner in data retention mode. Independent of enhancing the tunnel-oxide quality, the data retention characteristics are improved by designing a cell transistor that isolates the region where Fowler-Nordheim stress mainly occurs in tunnel oxide away from STI corner. Experimental results show that VTH shift is reduced by 0.3 V or more in retention mode as the tunneling is separated from the isolation edge.

The Effect of Trapped Charge Distributions on Data Retention Characteristics of nand Flash Memory Cells

As the scaling in NAND Flash Memory is progressed, the various interferences among the adjacent cells are more and more increased and the new phenomenon which is ignored until now has to be considered. In this paper, we will introduce the new program interference phenomenon which is generated between the program word line and the adjacent word lines along the bit-line. This new program interference is that the Vth's of the adjacent word lines along the bit-line are decreased while a word line is programming. Because this phenomenon is severely aggravated as the gate space is decreased, we have to consider this program interference for the future technology nodes.

New scaling limitation of the floating gate cell in NAND Flash Memory

A 3.3-V 16-Mb nonvolatile memory having operation virtually identical to DRAM with package pin compatibility has been developed. Read and write operations are fully DRAM compatible except for a longer RAS precharge time after write. Fast random access time of 63 ns with the NAND flash memory cell is achieved by using a hierarchical row decoder scheme and a unique folded bit-line architecture which also allows bit-by-bit program verify and inhibit operation. Fast page mode with a column address access time of 21 ns is achieved by sensing and latching 4 k cells simultaneously. To allow byte alterability, nonvolatile restore operation with self-contained erase is developed. Self-contained erase is word-line based, and increased cell disturb due to the word-line based erase is relaxed by adding a boosted bit-line scheme to a conventional self-boosting technique. The device is fabricated in a 0.5-/spl mu/m triple-well, p-substrate CMOS process using two-metal and three-poly interconnect layers. A resulting die size is 86.6 mm/sup 2/, and the effective cell size including the overhead of string select transistors is 2.0 /spl mu/m/sup 2/.

Kang-Deog Suh

Papers

A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme

Nonvolatile semiconductor memory device and an optimizing programming method thereof

The Effect of Trapped Charge Distributions on Data Retention Characteristics of nand Flash Memory Cells

New scaling limitation of the floating gate cell in NAND Flash Memory

A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using a NAND flash memory technology