You must turn in your code as well as output files. Please generate a report that contains the code and ouput in a single readable format. Getting Started  You may want to download Irfanview image viewing software. It handles pretty much any image type, lets you convert, and provides batch processing.  Download the sample images from the class website. The following question operates on the city.jpg image. (a) Perform image smoothing using a 7×7 averaging filter and a Gaussian filter with σ = 0.5 and 3. Compare the outputs. (b) Perform edge enhancement using the Sobel operator (Matlab's default parameters). Repeat using the Laplacian and Laplacian of Guassian operators. Compare the outputs 2. Frequency Domain Filtering The following question operates on the city.jpg image. (a) Find the Fourier transform of the image. Be sure to center the frequencies. (b) Perform image smoothing in the frequency domain using the filters defined in the previous problem. Compare the output images from the two methods (spatial and frequency) and the time for operation. (c) Perform edge enhancement using the filters defined in the previous problem. (d) Define a lowpass filter in the frequency domain with radius of 1/4 the height. Show the result. Repeat with a similar sized Guassian and compare the results. Give the σ parameter you used and show the output transform image. (e) Repeat with a rectangular filter with the same dimension as the ideal lowpass. Compare the results between the ideal filter and the rectangular approximation. 3. Canny Edge Detection (a) Give the convolution kernels for determining the gradient. You may examine the function gradient.m to help with the explanation. (It may be easiest to apply the gradient to an impulse and inspect the results. (b) Implement the simplified version of the Canny edge detector (single scale). The syntax of the function should be where E contains the detected edges, M the smoothed gradient magnitude, A contains the gradient angle, I is the input image, sig is the σ parameter for the smoothing filter, and tau= [τ h , τ l ] is the two element vector containing the hysteresis thresholds. See Algorithm 6.4 for non-maximal suppression and Algorithm 6.5 for hysteresis thresh-olding. (It may be more efficient to implement the hysteresis as edge tracking)

http://ieeexplore.ieee.org/iel5/5/31355/01457626.pdf

Multidimensional digital signal processing

This paper presents an error compensation method for a modified Booth fixed-width multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulations, it is shown that quantization error can be reduced up to 50% by the proposed error compensation method compared with the existing method with approximately the same hardware overhead in the bias generation circuit. It is also shown that the proposed method leads to up to 35% reduction in area and power consumption of a multiplier compared with the ideal multiplier.

Design of low-error fixed-width modified booth multiplier

The differential evolution (DE) algorithm is a new heuristic approach with three main advantages: it finds the true global minimum of a multimodal search space regardless of the initial parameter values, it has fast convergence, and it uses only a few control parameters. The DE algorithm, which has been proposed particularly for numeric optimization problems, is a population-based algorithm like the genetic algorithms and uses similar operators: crossover, mutation, and selection. In this work, the DE algorithm has been applied to the design of digital finite impulse response filters, and its performance has been compared to that of the genetic algorithm and least squares method.

Design of Digital FIR Filters Using Differential Evolution Algorithm

In this paper, a new design concept that engaged accuracy as a design parameter is proposed. By introducing accuracy as a design parameter, the bottleneck of conventional digital IC design techniques can be breakthrough to improve on the performances of power consumption and speed. The aim is to fulfill the need for high performance basic sequential elements with low-power dissipation which is steadily growing.

Low-power high-speed multiplier for error-tolerant application

A wideband CMOS low noise amplifier (LNA) with single-ended input and output employing noise and IM2 distortion cancellation for a digital terrestrial and cable TV tuner is presented. By adopting a noise canceling structure combining a common source amplifier and a common gate amplifier by current amplification, the LNA obtains a low noise figure and high IIP3. IIP2 as well as IIP3 of the LNA is important in broadband systems, especially digital terrestrial and cable TV applications. Accordingly, in order to overcome the poor IIP2 performance of conventional LNAs with single-ended input and output and avoid the use of external and bulky passive transformers along with high sensitivity, an IM2 distortion cancellation technique exploiting the complementary RF performance of NMOS and PMOS while retaining thermal noise canceling is adopted in the LNA. The proposed LNA is implemented in a 0.18 mum CMOS process and achieves a power gain of 14 dB, an average noise figure of 3 dB, an IIP3 of 3 dBm, an IIP2 of 44 dBm at maximum gain, and S11 of under -9 dB in a frequency range from 50 MHz to 880 MHz. The power consumption is 34.8 mW at 2.2 V and the chip area is 0.16 mm2.

/pdf/a-wideband-cmos-low-noise-amplifier-employing-noise-and-im2-4fnzfoy26w.pdf

A Wideband CMOS Low Noise Amplifier Employing Noise and IM2 Distortion Cancellation for a Digital TV Tuner

An area-efficient parallel sign-magnitude multiplier that receives two N-bit numbers and produces an N-bit product, referred to as a truncated multiplier, is described. The quantization of the product to N bits is achieved by omitting about half the adder cells needed to add the partial products but in order to keep the quantization error to a minimum, probabilistic biases are obtained and are then fed to the inputs of the retained adder cells. The truncated multiplier requires approximately 50% of the area of a standard parallel multiplier. The paper then shows that this design strategy can also be applied for the design of two's-complement multipliers. The paper concludes with the application of the truncated multiplier for the implementation of a digital filter and it is shown that the signal-to-noise ratio of the digital filter using a truncated multiplier is better than that using a standard multiplier.

Area-efficient multipliers for digital signal processing applications

A method for the design of allpass filters is described. In this method, an error reflecting the difference between the desired phase response and the phase response of the practical allpass filter is formulated in a quadratic form. The coefficients are obtained by solving a system of linear equations involving the sum of a Toeplitz and an Hankel matrix.

Weighted least-squares design of recursive allpass filters

A two-channel time-interleaved analog-to-digital converter (TIADC) system that provides for estimation and correction of offset, gain, and sample-time errors. Error in the offsets of the two ADCs that form the TIADC produces a spurious signal at the Nyquist frequency that can be used to minimize the difference of offsets of the ADCs. The difference in gain between the two ADCs produces spurious signals reflected around the Nyquist frequency whose magnitudes can be reduced by minimizing the difference in signal power between the two ADCs. An Automatic Gain Control loop corrects the scaling of the input signal due to the average of the gains of the ADCs. Phase error produces spurious signals reflected around the Nyquist frequency that are π/2 out of phase with those due to the gain error. Minimizing the difference between the correlation of consecutive signals from the ADCs reduces the magnitude of these image tones.

Error estimation and correction in a two-channel time-interleaved analog-to-digital converter

A multipurpose TV tuner front-end implemented in 0.35/spl mu/m BiCMOS technology is presented. It employs a dual-conversion topology and a fully integrated RF automatic gain control loop. The tuner front-end achieves -68dB composite-triple beat (CTB) distortion and a noise figure of 6.8-7.4dB in a 50-870Mhz input frequency range. In addition, the front-end is interfaced with a companion chip, which contains a high dynamic range ADC combined with programmable digital filters to accommodate multi-standard operation.

A dual-conversion tuner for multi-standard terrestrial and cable reception

Techniques for correcting component mismatches in an M-channel time-interleaved Analog to Digital Converter (ADC). In order to obtain an error measure for offset, gain or phase, errors, outputs from each ADC are either summed or averaged over N o samples. Calling each of the sums or averages as X k where k=1, 2, . . . , M, there are M such values as a result. A single value representing the mean of these M values, X mean , is chosen as a reference value. The offset, gain and phase errors for the M different ADCs are then obtained from X k −X mean . The sign of each offset error, i.e., sign (X k −X mean ), is then used to drive an adaptive algorithm whose output represents an offset correction value for the corresponding ADC. The offset, gain, and phase correction outputs from the adaptive algorithm is fed to an array of Digital-to-Analog converters (DACs) whose outputs are voltages or currents that directly or indirectly controls the offset, gain or phase setting of each individual ADC. Thus, there are M different offset, gain and phase error signals and M different adaptive algorithms operating in conjunction with M different DACs providing offset control signals to M different ADCs. In certain embodiments, spur frequencies can be reduced with the use of notch filters.

Sunder S. Kidambi

Papers

Area-efficient multipliers for digital signal processing applications

Weighted least-squares design of recursive allpass filters

Error estimation and correction in a two-channel time-interleaved analog-to-digital converter

A dual-conversion tuner for multi-standard terrestrial and cable reception

Calibration of offset, gain and phase errors in M-channel time-interleaved analog-to-digital converters