S
Sunil Sudhakaran
Researcher at Nvidia
Publications - 16
Citations - 197
Sunil Sudhakaran is an academic researcher from Nvidia. The author has contributed to research in topics: Noise & Memory controller. The author has an hindex of 6, co-authored 16 publications receiving 141 citations.
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Patent
8b/9b encoding for reducing crosstalk on a high speed parallel bus
TL;DR: The 8b/9b encoding scheme as mentioned in this paper enables a data word to be encoded using code words, each of the valid code words does not include any three consecutive bits having a logic level of logic high (i.e., "1") and represent transition vectors for consecutive symbols transmitted over the high speed parallel bus.
Journal ArticleDOI
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator
John W. Poulton,John Wilson,Walker J. Turner,Brian Zimmer,Xi Chen,Sudhir S. Kudva,Sanquan Song,Stephen G. Tell,Nikola Nedovic,Wenxu Zhao,Sunil Sudhakaran,C. Thomas Gray,William J. Dally +12 more
TL;DR: This paper describes a short-reach serial link to connect chips mounted on the same package or on neighboring packages on a printed circuit board (PCB) that employs an energy-efficient, single-ended ground-referenced signaling scheme and employs a novel power supply regulation scheme at both ends.
Proceedings ArticleDOI
A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator
John Wilson,Walker J. Turner,John W. Poulton,Brian Zimmer,Xi Chen,Sudhir S. Kudva,Sanquan Song,Stephen G. Tell,Nikola Nedovic,Wenxu Zhao,Sunil Sudhakaran,C. Thomas Gray,William J. Dally +12 more
TL;DR: The combination of signal integrity challenges and production margining requires increased amplitude, equalization, ESD protection, and PVT-tolerant circuit design techniques.
Proceedings ArticleDOI
Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects
Walker J. Turner,John W. Poulton,John Wilson,Xi Chen,Stephen G. Tell,Matthew Fojtik,Thomas Hastings Greer,Brian Zimmer,Sanquan Song,Nikola Nedovic,Sudhir S. Kudva,Sunil Sudhakaran,Rizwan Bashirullah,Wenxu Zhao,William J. Dally,C. Thomas Gray +15 more
TL;DR: Various methodologies compatible with GRS are presented, including design considerations and various circuit architectures, which enables simple but efficient signaling across on-chip communication fabrics, off-chip organic packages, and off-package printed circuit boards.
Proceedings ArticleDOI
Power delivery network design and modeling for High Bandwidth Memory (HBM)
TL;DR: In this article, a modeling method to consider simulation switching noise of HBM and its impact on HBM timing is described, which combines partial element equivalent circuit model for power delivery network and S-parameters based HBM channel model together in HBM studies.