W
Walker J. Turner
Researcher at Nvidia
Publications - 16
Citations - 203
Walker J. Turner is an academic researcher from Nvidia. The author has contributed to research in topics: Computer science & Phase-locked loop. The author has an hindex of 4, co-authored 10 publications receiving 77 citations.
Papers
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Proceedings ArticleDOI
ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks
TL;DR: ParaGraph: a graph neural network model to predict net parasitics and device parameters by converting circuit schematics into graphs and leveraging key modeling techniques based on GraphSage, Relation GCN and Graph Attention Networks increases model accuracy over a large range of prediction values.
Journal ArticleDOI
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator
John W. Poulton,John Wilson,Walker J. Turner,Brian Zimmer,Xi Chen,Sudhir S. Kudva,Sanquan Song,Stephen G. Tell,Nikola Nedovic,Wenxu Zhao,Sunil Sudhakaran,C. Thomas Gray,William J. Dally +12 more
TL;DR: This paper describes a short-reach serial link to connect chips mounted on the same package or on neighboring packages on a printed circuit board (PCB) that employs an energy-efficient, single-ended ground-referenced signaling scheme and employs a novel power supply regulation scheme at both ends.
Proceedings ArticleDOI
A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator
John Wilson,Walker J. Turner,John W. Poulton,Brian Zimmer,Xi Chen,Sudhir S. Kudva,Sanquan Song,Stephen G. Tell,Nikola Nedovic,Wenxu Zhao,Sunil Sudhakaran,C. Thomas Gray,William J. Dally +12 more
TL;DR: The combination of signal integrity challenges and production margining requires increased amplitude, equalization, ESD protection, and PVT-tolerant circuit design techniques.
Proceedings ArticleDOI
Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects
Walker J. Turner,John W. Poulton,John Wilson,Xi Chen,Stephen G. Tell,Matthew Fojtik,Thomas Hastings Greer,Brian Zimmer,Sanquan Song,Nikola Nedovic,Sudhir S. Kudva,Sunil Sudhakaran,Rizwan Bashirullah,Wenxu Zhao,William J. Dally,C. Thomas Gray +15 more
TL;DR: Various methodologies compatible with GRS are presented, including design considerations and various circuit architectures, which enables simple but efficient signaling across on-chip communication fabrics, off-chip organic packages, and off-package printed circuit boards.
Proceedings ArticleDOI
Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization
TL;DR: In this article, the authors proposed an improved surrogate performance model using parasitic graph embeddings from the pre-trained parasitic prediction network, which has 20% better R2 prediction score and improves optimization convergence by 3.7 times and 2.1 times compared to conventional Gaussian process regression and neural network based Bayesian linear regression.