A recycling amplifier architecture based on the folded cascode transconductance amplifier is described. The proposed amplifier delivers an appreciably enhanced performance over that of the conventional folded. This is achieved by using previously idle devices in the signal path, which results in an enhanced transconductance, gain, and slew rate. Moreover, the input referred noise and offset analyses are included to demonstrate that the proposed modifications have no adverse effects on these design metrics. Transistor-level simulations and experimental results in TSMC 0.18 mum CMOS process confirm the theoretical results. When compared to the conventional folded cascode, and for the same area and power budgets, the proposed amplifier has almost twice the bandwidth (134.2 MHz versus 70.7 MHz) and better than twice the slew rate (94.1 V/mus versus 42.1 V/mus) while driving the same 5.6 pF load. Also a gain enhancement of 7.6 dB is observed.

The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier

This paper presents a tutorial overview of ΣΔ modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless telecom systems.

Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

At the turn of this century, there was widespread concern that the performance of analog-to-digital converters (ADCs) might have reached a saturation point and would, in fact, deteriorate as we began to scale into deep submicron CMOS technology. The past 15 years of innovation have clearly refuted such fears. Driven by a combination of application pull, architectural modifications, and relentless optimization, we have seen steady improvements in several key performance metrics.

The Race for the Extra Decibel: A Brief Review of Current ADC Performance Trajectories

This paper presents a new multi-loop delta-sigma modulator which overcomes the necessity of high DC gain opamps that were needed in previous multi-loop modulators. Enabling the use of low gain opamps also allows low-voltage operation due to the reduced number of transistors between the power supply rails. In addition, all the digital filters are removed from the output of this modulator to minimize the overall system requirement. Instead, an in-loop digital addition facilitates the desired noise transfer functions of both loops. This combines stability advantage of the multi-loop structure with relaxed circuit requirement of the single-loop modulator. A fourth order modulator is implemented in a 0.18 mum CMOS technology to demonstrate this concept. Measurement results show that, with open-loop opamp gain of less than 35 dB, the implemented prototype IC achieves over 74 dB SNDR at an oversampling ratio of 16. The sampling frequency is 20 MHz and the total power dissipation is 3.2 mW at 1.2 V supply.

74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain

This paper describes a wideband high-linearity ?? ADC. It uses noise coupling combined with time interleaving. Two versions of a two-channel time-interleaved noise-coupled ?? ADC were realized in a 0.18-?m CMOS technology. Noise coupling between the channels increases the effective order of the noise-shaping loops, provides dithering, and prevents tone generation in all loops. Time interleaving enhances the effects of noise coupling. Using a 1.5 V supply, the device achieved excellent linearity (SFDR>100 dB, THD=-98 dB) and an SNDR of 79 dB in a 4.2 MHz signal band.

A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$ 98 dB THD, and 79 dB SNDR

A new Δ-Σ modulator is proposed. Its operation is similar to that of a multi-stage noise-shaping structure but requires no digital noise cancellation filters. Thus, the need for matching required between analogue and digital filters is eliminated. Simulation results and mathematical analysis demonstrate the effectiveness of this structure.

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Sturdy MASH /spl Delta//spl Sigma/ modulator

A two-channel time-interleaved second-order sigma-delta modulator for broadband applications including asymmetrical digital subscriber line (ADSL) is presented. The proposed two-channel SigmaDelta modulator uses a single integrator channel which does not require additional active elements for the quantizer input generation, since the integrator outputs are directly used as the input of the quantizers. As a result, the entire modulator can be implemented using only two op-amps, which is beneficial for both power consumption and area. Furthermore, this architecture is robust to channel mismatch effects and can operate with a simple clocking scheme. The SigmaDelta modulator achieves a dynamic range of 85 dB over a 1.1-MHz signal bandwidth with an effective clock frequency of 132 MHz. The circuit is implemented in 0.18-mum CMOS technology using metal-insulator-metal capacitors. The total power consumption of the SigmaDelta modulator is 5.4mW from a 1.8-V supply and occupies an active area of 1.1 mm2

A Power-Efficient Two-Channel Time-Interleaved ΣΔ Modulator for Broadband Applications

A time-to-digital converter (TDC) employs a phase-reference second-order continuous-time delta-sigma modulator to achieve high resolution and low power. The modulator operates on the phase of the input signal and generates an equivalent noise-shaped one-bit output data stream. Fabricated in an LP 90nm CMOS process, the prototype TDC achieves better than 2.4ps resolution over a 3.2ns range in a 1MHz signal bandwidth while consuming 2.1mW from a 1.2V supply.

A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth

A delta-sigma analog-to-digital converter employs zero-crossing-based integrators to achieve low power operation at 50MHz sampling rate. Switched resistors, used as current sources, provide good dynamic current matching, eliminating the need for common-mode feedback circuits. The effect of the switched resistors on the linearity of the zero-crossing-based integrator is discussed. Also, a unidirectional 2-phase charging scheme is proposed to improve input signal swing and reduce overshoot voltage. Test chip implemented in a 45nm LP Digital CMOS achieves 54.3dB DR, 52.5dB SNR, and 47.7dB SNDR at 0.833MHz input while dissipating 630μ;W from a 1.1V supply.

Sunwoo Kwon

Papers

74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain

Sturdy MASH /spl Delta//spl Sigma/ modulator

A Power-Efficient Two-Channel Time-Interleaved ΣΔ Modulator for Broadband Applications

A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth

A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS