The Transmission Control Protocol.

Networks-on-Chip constitute the interconnection architecture of future, massively parallel multiprocessors that assemble hundreds to thousands of processing cores on a single chip. Their integration is enabled by ongoing miniaturization of chip manufacturing technologies following Moore's Law. It comes with the downside of the circuit elements' increased susceptibility to failure. Research on fault-tolerant Networks-on-Chip tries to mitigate partial failure and its effect on network performance and reliability by exploiting various forms of redundancy at the suitable network layers. The article at hand reviews the failure mechanisms, fault models, diagnosis techniques, and fault-tolerance methods in on-chip networks, and surveys and summarizes the research of the last ten years. It is structured along three communication layers: the data link, the network, and the transport layers. The most important results are summarized and open research problems and challenges are highlighted to guide future research on this topic.

Methods for fault tolerance in networks-on-chip

The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity even if network components are out of service due to faults, which will appear at an increasing rate with future chip technology nodes. This paper is based on a new, fine-grained functional fault model and a corresponding distributed fault diagnosis method that facilitate determining the fault status of individual NoC switches and their adjacent communication links. Whereas previous work on network fault-tolerance assume switches to be either available or fully out of service, we present a novel adaptive routing algorithm that employs the remaining functionality of partly defective switches. Using diagnostic information, transient faults are handled with a retransmission scheme that avoids the latency penalty of end-to-end repeat requests. Thereby, graceful degradation of NoC communication performance can be achieved even under high failure rates.

Fault Tolerant Network on Chip Switching With Graceful Performance Degradation

Continuing decrease in the feature size of integrated circuits leads to increases in susceptibility to transient and permanent faults. This paper proposes a fault-tolerant solution for a bufferless network-on-chip, including an on-line fault-diagnosis mechanism to detect both transient and permanent faults, a hybrid automatic repeat request, and forward error correction link-level error control scheme to handle transient faults and a reinforcement-learning-based fault-tolerant deflection routing (FTDR) algorithm to tolerate permanent faults without deadlock and livelock. A hierarchical-routing-table-based algorithm (FTDR-H) is also presented to reduce the area overhead of the FTDR router. Synthesized results show that, compared with the FTDR router, the FTDR-H router can reduce the area by 27% in an 88 network. Simulation results demonstrate that under synthetic workloads, in the presence of permanent link faults, the throughput of an 8 8 network with FTDR and FTDR-H algorithms are 14% and 23% higher on average than that with the fault-on-neighbor (FoN) aware deflection routing algorithm and the cost-based deflection routing algorithm, respectively. Under real application workloads, the FTDR-H algorithm achieves 20% less hop counts on average than that of the FoN algorithm. For transient faults, the performance of the FTDR router can achieve graceful degradation even at a high fault rate. We also implement the fault-tolerant deflection router which can achieve 400 MHz in TSMC 65-nm technology.

Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router

Given the spatial and temporal randomness of soft and permanent errors in the state-of-the-art system-on-chips (SoCs), dynamic routing algorithms that can adapt themselves accordingly are highly required for network-on-chip (NoC) applications. In this paper, we present a new dynamic routing algorithm for NoC applications that has the ability to locate and deal with both static and dynamic permanent failures and distinguish them from soft errors. In addition, our presented algorithm has the advantage of distributing the load over the whole network by considering the stress factors. Simulation results demonstrate the advantage of our routing algorithm in terms of functionality, latency, and energy consumption compared to directed flooding based fault tolerant routing algorithms in the presence of both soft errors and permanent faults. Our algorithm can achieves 1.95 times less latency and consumes 3.15 times less energy consumption on average.

A fault-aware dynamic routing algorithm for on-chip networks

Network on chips (NoC) have emerged as a feasible solution to handle growing number of communicating components on a single chip. The scalability of chips however increases the probability of errors, hence making reliability a major issue in scaling chips. We hereby propose a comprehensive fault tolerant mechanism for packet based NoCs to deal with packet losses or corruption due to transient faults as well as a dynamic routing mechanism to deal with permanent link and/or router failure on-chip

A Fault tolerant mechanism for handling Permanent and Transient Failures in a Network on Chip

Recent advances in the silicon technology is enabling the VLSI chips to accommodate billions of transistors; leading toward incorporating hundreds of heterogeneous components on a single chip. However, it has been observed that the scalability of chips is posing grave problems for the current interconnect architecture which is unable to cope with the growing number of components on a chip. To remedy the inefficiency of buses, researchers have explored the area of computer networks besides exploring parallel computing to come up with viable solutions for billion transistor chips. The outcome is a novel and scalable communication paradigm for future System on Chips (SoCs) called as Network on Chips (NoC). However, as the chip scales, the probability of both permanent and temporary faults is also increasing, making Fault Tolerance (FT) a key concern in scaling chips. Alpha particle emissions, Gaussian noise on channels are some of the reasons which introduce transient faults in the data. Besides that, due to electromigration of conductors, corrosion or aging factors, on-chip modules or links may suffer permanent damage. This paper proposes a comprehensive solution to deal with both permanent and transient errors affecting the VLSI chips. On the one hand we present an efficient packet retransmission mechanism to deal with packet corruption or loss due to transient faults. On the other hand, we propose a deterministic routing mechanism which routes packets on alternate paths when a communication link or a router suffers permanent failure.

An efficient fault tolerant mechanism to deal with permanent and transient failures in a network on chip

Properly reacting to congestion is known to be a requirement for maintaining the stability of the Internet; in addition, UDP based applications should do so for their own sake if they are delay- or loss-sensitive. We measured the responsiveness of the three popular streaming media applications RealPlayer, Windows MediaPIayer and Quicktime with a varying amount of cross traffic and present a comparison of the results.

An empirical study of the congestion response of RealPlayer, Windows MediaPlayer and Quicktime

The ns network simulator is a common tool frequently used for teaching the fundamentals of computer networks. However, our experience with students has shown that writing long ns scripts is not appreciated by them. Hence, we used a custom-made visualization tool — NSBM — where topologies are created using a mouse and then the TCL script is generated automatically. The tool is interactive and has an easy interface to create topologies and define agents and protocols that govern the communication setup. The feedback of students was relatively encouraging as the majority found it to be useful in learning networking fundamentals.

Sven Hessler

Papers

A Fault tolerant mechanism for handling Permanent and Transient Failures in a Network on Chip

An efficient fault tolerant mechanism to deal with permanent and transient failures in a network on chip

An empirical study of the congestion response of RealPlayer, Windows MediaPlayer and Quicktime

Network Simulation By Mouse (NSBM): A GUI Approach for Teaching Computer Networks with the ns Simulator

Seamless transport service selection by deploying a middleware