In this paper, an efficient very large scale integration (VLSI) architecture, called flipping structure, is proposed for the lifting-based discrete wavelet transform. It can provide a variety of hardware implementations to improve and possibly minimize the critical path as well as the memory requirement of the lifting-based discrete wavelet transform by flipping conventional lifting structures. The precision issues are also analyzed. By case studies of the JPEG2000 default lossy (9,7) filter, an integer (9,7) filter, and the (6,10) filter, the efficiency of the proposed flipping structure is demonstrated.

/pdf/flipping-structure-an-efficient-vlsi-architecture-for-19bua53j9p.pdf

Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform

The lifting scheme reduces the computational complexity of the discrete wavelet transform (DWT) by factoring the wavelet filters into cascades of simple lifting steps that process the input samples in pairs. We propose four compact and efficient hardware architectures for implementing lifting-based DWTs, namely, one-dimensional (1-D) and two-dimensional (2-D) versions of what we call recursive and dual scan architectures. The 1-D recursive architecture exploits interdependencies among the wavelet coefficients by interleaving, on alternate clock cycles using the same datapath hardware, the calculation of higher order coefficients along with that of the first-stage coefficients. The resulting hardware utilization exceeds 90% in the typical case of a five-stage 1-D DWT operating on 1024 samples. The 1-D dual scan architecture achieves 100% datapath hardware utilization by processing two independent data streams together using shared functional blocks. The recursive and dual scan architectures can be readily extended to the 2-D case. The 2-D recursive architecture is roughly 25% faster than conventional implementations, and it requires a buffer that stores only a few rows of the data array instead of a fixed fraction (typically 25% or more) of the entire array. The 2-D dual scan architecture processes the column and row transforms simultaneously, and the memory buffer size is comparable to existing architectures.

Efficient architectures for 1-D and 2-D lifting-based wavelet transforms

In this paper, we construe key factors in design and evaluation of image processing algorithms on the massive parallel graphics processing units (GPUs) using the compute unified device architecture (CUDA) programming model. A set of metrics, customized for image processing, is proposed to quantitatively evaluate algorithm characteristics. In addition, we show that a range of image processing algorithms map readily to CUDA using multiview stereo matching, linear feature extraction, JPEG2000 image encoding, and nonphotorealistic rendering (NPR) as our example applications. The algorithms are carefully selected from major domains of image processing, so they inherently contain a variety of subalgorithms with diverse characteristics when implemented on the GPU. Performance is evaluated in terms of execution time and is compared to the fastest host-only version implemented using OpenMP. It is shown that the observed speedup varies extensively depending on the characteristics of each algorithm. Intensive analysis is conducted to show the appropriateness of the proposed metrics in predicting the effectiveness of an application for parallel implementation.

https://image.inha.ac.kr/paper/TPDS10PIK.pdf

Design and Performance Evaluation of Image Processing Algorithms on GPUs

In this paper, we propose a high-performance and memory-efficient pipeline architecture which performs the one-level two-dimensional (2-D) discrete wavelet transform (DWT) in the 5/3 and 9/7 filters. In general, the internal memory size of 2-D architecture highly depends on the pipeline registers of one-dimensional (1-D) DWT. Based on the lifting-based DWT algorithm, the primitive data path is modified and an efficient pipeline architecture is derived to shorten the data path. Accordingly, under the same arithmetic resources, the 1-D DWT pipeline architecture can operate at a higher processing speed (up to 200 MHz in 0.25-/spl mu/m technology) than other pipelined architectures with direct implementation. The proposed 2-D DWT architecture is composed of two 1-D processors (column and row processors). Based on the modified algorithm, the row processor can partially execute each row-wise transform with only two column-processed data. Thus, the pipeline registers of 1-D architecture do not fully turn into the internal memory of 2-D DWT. For an N/spl times/M image, only 3.5N internal memory is required for the 5/3 filter, and 5.5N is required for the 9/7 filter to perform the one-level 2-D DWT decomposition with the critical path of one multiplier delay (i.e., N and M indicate the height and width of an image). The pipeline data path is regular and practicable. Finally, the proposed architecture implements the 5/3 and 9/7 filters by cascading the three key components.

https://ir.nctu.edu.tw:443/bitstream/11536/13021/1/000233764000010.pdf

A high-performance and memory-efficient pipeline architecture for the 5/3 and 9/7 discrete wavelet transform of JPEG2000 codec

This paper describes an area and power-efficient VLSI approach for implementing the discrete wavelet transform on streaming multielectrode neurophysiological data in real time. The VLSI implementation is based on the lifting scheme for wavelet computation using the symmlet4 basis with quantized coefficients and integer fixed-point data precision to minimize hardware demands. The proposed design is driven by the need to compress neural signals recorded with high-density microelectrode arrays implanted in the cortex prior to data telemetry. Our results indicate that signal integrity is not compromised by quantization down to 5-bit filter coefficient and 10-bit data precision at intermediate stages. Furthermore, results from analog simulation and modeling show that a hardware-minimized computational core executing filter steps sequentially is advantageous over the pipeline approach commonly used in DWT implementations. The design is compared to that of a B-spline approach that minimizes the number of multipliers at the expense of increasing the number of adders. The performance demonstrates that in vivo real-time DWT computation is feasible prior to data telemetry, permitting large savings in bandwidth requirements and communication costs given the severe limitations on size, energy consumption and power dissipation of an implantable device.

/pdf/a-scalable-wavelet-transform-vlsi-architecture-for-real-time-5dfctync39.pdf

A Scalable Wavelet Transform VLSI Architecture for Real-Time Signal Processing in High-Density Intra-Cortical Implants

We propose an architecture that performs the forward and inverse discrete wavelet transform (DWT) using a lifting-based scheme for the set of seven filters proposed in JPEG2000. The architecture consists of two row processors, two column processors, and two memory modules. Each processor contains two adders, one multiplier, and one shifter. The precision of the multipliers and adders has been determined using extensive simulation. Each memory module consists of four banks in order to support the high computational bandwidth. The architecture has been designed to generate an output every cycle for the JPEG2000 default filters. The schedules have been generated by hand and the corresponding timings listed. Finally, the architecture has been implemented in behavioral VHDL. The estimated area of the proposed architecture in 0.18-/spl mu/ technology is 2.8 nun square, and the estimated frequency of operation is 200 MHz.

/pdf/a-vlsi-architecture-for-lifting-based-forward-and-inverse-3wtkyokaha.pdf

A VLSI architecture for lifting-based forward and inverse wavelet transform

This survey of spine surgeons aimed to determine the prevalence of neck pain and identify the associated risk factors. The prevalence of neck pain has been reported in various medical sub-specialities including laparoscopy surgeons, dentists, plastic surgeons, ophthalmologist, urologist and orthopaedic surgeons. However, the literature is lacking on prevalence and risk factors for neck pain in spine surgeons.A survey questionnaire containing demographic, Neck pain and work practice details was administered to 300 spine surgeons (members of an online group) via text message and e-mail.One hundred and eighty surgeons responded to the survey (response rate, 60%). Three spine surgeons had previous cervical spine surgeries. The 1-month prevalence rate of neck pain was 74.4% (134/180 surgeons). One hundred and eighteen surgeons (88%) reported only neck pain, 16 surgeons (11.9%) had neck pain with radicular arm pain. Only 20.5% of surgeons used a loupe, 18% of surgeons used a microscope, and 24% of surgeons used operating table height at umbilicus during surgery. There was no significant difference between the mean age (p = 0.65), work experience (p = 0.8), time spent in surgery (p = 0.7), and operating table height preference (p = 0.4) when symptomatic and asymptomatic groups were compared. However, a significantly greater percentage of surgeons had a sedentary lifestyle (p = 0.002) & used loupes as compared to microscopes (p = 0.04) in the symptomatic group. There was significant correlation between the surgeon's lifestyle & use of loupe and the incidence of neck pain.Spine surgeons have a higher prevalence of neck pain than general populations and surgeons from other specialties. Considering the high prevalence of neck pain, general health, work, and ergonomic guidelines and recommendations must be formulated to help prevent and decrease the burden of neck pain among spine surgeons. 

T. Acharya

Papers

A VLSI architecture for lifting-based forward and inverse wavelet transform

Prevalence and risk factors of neck pain in spine surgeons - Are we our own patients?