As digital circuits become faster and more powerful, direct radiation from the power bus of their printed circuit boards (PCB) becomes a major concern for electromagnetic compatibility engineers. In such multilayer PCBs, the power and ground planes act as radiating microstrip patch antennas, where radiation is caused by fringing electric fields at board edges. In this paper, we introduce an effective method for suppressing PCB radiation from their power bus over an ultrawide range of frequencies by using metallo-dielectric electromagnetic band-gap structures. More specifically, this study focuses on the suppression of radiation from parallel-plate bus structures in high-speed PCBs caused by switching noise, such as simultaneous switching noise, also known as Delta-I noise or ground bounce. This noise consists of unwanted voltage fluctuations on the power bus of a PCB due to resonance of the parallel-plate waveguiding system created by the power bus planes. The techniques introduced here are not limited to the suppression of switching noise and can be extended to any wave propagation between the plates of the power bus. Laboratory PCB prototypes were fabricated and tested revealing appreciable suppression of radiated noise over specific frequency bands of interest, thus, testifying to the effectiveness of this concept.

Electromagnetic interference (EMI) reduction from printed circuit boards (PCB) using electromagnetic bandgap structures

Electromagnetic interference (EMI) issues are expected to be crucial for next-generation system-on-package (SOP) integrated high-performance digital LSIs and for radio frequency (RF) and analog circuits. Ordinarily in SOPs, high-performance digital LSIs are sources of EMI, while RF and analog circuits are affected by EMI (victims). This paper describes the following aspects of EMI in SOPs: 1) die/package-level EMI; 2) substrate-level EMI; 3) electromagnetic modeling and simulation; and 4) near electromagnetic field measurement. First, LSI designs are discussed with regard to radiated emission. The signal-return path loop and switching current in the power/ground line are inherent sources of EMI. The EMI of substrate, which work as coupling paths or unwanted antennas, is described. Maintaining the return current path is an important aspect of substrate design for suppressing EMI and for maintaining signal integrity (SI). In addition, isolating and suppressing the resonance of the DC power bus in a substrate is another important design aspect for EMI and for power integrity (PI). Various electromagnetic simulation methodologies are introduced as indispensable design tools for achieving high-performance SOPs without EMI problems. Measurement techniques for near electric and magnetic fields are explained, as they are necessary to confirm the appropriateness of designs and to investigate the causes of EMI problems. This paper is expected to be useful in the design and development of SOPs that take EMI into consideration.

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Electromagnetic interference (EMI) of system-on-package (SOP)

The radiation from power-bus structures on high-speed printed circuit boards due to the switching noise current of digital integrated circuits is investigated. The study is based on an analytical cavity-resonator model for a rectangular parallel-plate structure. Based on the application of the field-equivalence principle, the radiated field is calculated from the electric edge-field distribution. For typical board dimensions, several cavity-mode resonances occur within the typical frequency range of interest, leading to relatively high maximum values for radiated emission. The evaluation of the radiation patterns reveals that all (0, nth) resonances have equal maximum amplitudes in the whole mode spectrum. This allows the setting up of an engineering equation for quantifying the noise-current-related maximum radiated field strength, including the dielectric and ohmic loss. Among all geometrical and material parameters, the dielectric thickness is one of the most effective ones to control radiated emission. The theoretical results are well confirmed by accurate measurements carried out in an anechoic room.

The radiation of a rectangular power-bus structure at multiple cavity-mode resonances

This paper experimentally investigates the effectiveness of embedded capacitance for reducing power-bus noise in high-speed printed circuit board designs. Boards with embedded capacitance employ closely spaced power-return plane pairs separated by a thin layer of dielectric material. In this paper, test boards with four embedded capacitance materials are evaluated. Power-bus input impedance measurements and power-bus noise measurements are presented for boards with various dimensions and layer stack ups. Unlike discrete decoupling capacitors, whose effective frequency range is generally limited to a few hundred megahertz due to interconnect inductance, embedded capacitance was found to efficiently reduce power-bus noise over the entire frequency range evaluated (up to 5 GHz).

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Power-bus decoupling with embedded capacitance in printed circuit board design

Consideration of the higher order time derivatives of voltage and current transitions in power semiconductor devices enables the specification of “S-shaped” switching waveforms which offer an improved tradeoff between high-frequency EMI generation and switching losses. In comparison with the widely used first-order derivative trapezoidal switching waveform approximation, Fourier analysis of the proposed “S-shaped” waveform shows that it exhibits a 20 dB/dec steeper spectral gradient at high frequencies, resulting in a 20 dB greater reduction in high-frequency spectral content per decade increase in rise time. Numerical analysis of the proposed waveform shows that both peak and total RF power, employed as indicative EMI metrics, are reduced significantly with no increase in overall switching time. Experimental investigation of the effect of introducing a frequency-selective EMI transmission path shows that the overall trends in the relationships between time-domain waveform parameters and high-frequency spectral content are maintained, while the values of the waveform timing parameters which minimize the two EMI metrics are changed.

Analysis of Shaped Pulse Transitions in Power Electronic Switching Waveforms for Reduced EMI Generation

Power islands are often used to isolate devices that put noise on a power bus from devices that may be susceptible to power bus noise. At high frequencies however, the effectiveness of these islands depends on the implementation. This paper experimentally investigates the effectiveness of different power island structures at frequencies up to 3 GHz.

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Power bus noise reduction using power islands in printed circuit board designs

Power island structures are often employed for minimizing the propagation of high-frequency noise on DC power buses. The rationale is based on introducing a series impedance in the power plane to provide isolation of a noise source from the rest of the PCB design. The power island concept is investigated herein experimentally, to determine its noise mitigation attributes and limitations. A modeling approach that is suitable for arbitrary PCB island geometries including lumped SMT decoupling capacitors is also presented. The modeling and measurements indicate that island structures can achieve some degree of isolation under certain conditions.

/pdf/rf-isolation-using-power-islands-in-dc-power-bus-design-49vwderung.pdf

RF isolation using power islands in DC power bus design

This tutorial paper reviews the basic mechanisms by which signal voltages and currents on a printed circuit board produce unintentional radiated emissions.

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Printed circuit board EMI source mechanisms

The coupling between apertures or slots in airflow arrays is investigated numerically by means of the method of moments (MoM). Application to shielding enclosure design is of particular interest. Justification for a previously extracted simple empirical design approach for the relation between the number N and size a of apertures, and the shielding effectiveness /spl sim/Na/sup 3/ for an airflow aperture array is given. The coupling between slots is also investigated. The application limit of the empirical design approach is demonstrated.

/pdf/slot-and-aperture-coupling-for-airflow-aperture-arrays-in-3gm0leg6q6.pdf

Slot and aperture coupling for airflow aperture arrays in shielding enclosure designs

The adequacy of the DC power bus decoupling for CMOS devices can be determined if the effective board decoupling capacitance, the CMOS load capacitance, the CMOS power dissipation capacitance, the switching time, and the allowable bus noise voltage are known. A simple method is presented for estimating the effective decoupling capacitance. The load and power dissipation capacitance values are shown analytically and experimentally to be closely related to the transient current. The transient current and switching time are used to estimate the transient noise voltage on the power bus.

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T.H. Hubing

Papers

Power bus noise reduction using power islands in printed circuit board designs

RF isolation using power islands in DC power bus design

Printed circuit board EMI source mechanisms

Slot and aperture coupling for airflow aperture arrays in shielding enclosure designs

Designing power bus decoupling for CMOS devices