This index covers all technical items - papers, correspondence, reviews, etc. that appeared in this periodical during 2000, and items from previous years that were commented upon or corrected in 2000. In the case of magazines, departments and other items may be also covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author’s name. The primary entry includes the coauthors’ names, the title of the paper or other item, and its location, specified by the publica tion abbreviation, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author’s name, the publication abbreviation, month, and year, and inclusive pages. Subject cross-references are included to assist in find ing items of interest. Note that the item title is found only under the primary entry in the Author Index.

IEEE Signal Processing Magazine Vol. 17

Improved estimation performance using known linear constraints

Parallel saturating multioperand adders significantly improve the performance of global system for mobile (GSM) speech coders by giving compilers and assembly language programmers the ability to parallelize loops containing saturating dot products, while maintaining GSM compliant results. This paper presents four designs for parallel saturating multioperand adders. These designs have at most one carry-propagate adder on their critical delay path, yet produce the same results that would be obtained if the additions were performed serially with saturation after each addition. The four parallel designs offer tradeoffs in terms of area, worst case delay, and dot product latency. Compared to a 5-input serial design, the 5-input parallel designs have delays up to 3.51 times shorter.

/pdf/design-alternatives-for-parallel-saturating-multioperand-4cdg0hklfd.pdf

Design alternatives for parallel saturating multioperand adders

The processing delay is a serious constraint for speech communication. A one-way end-to-end delay of more than 150 ms can severely degrade the quality of real-time conversations. The components of the total system delay includes the speech frame size, the look ahead, other algorithmic delays, multiplexing delay, processing delay for computation, and transmission delay. At the transcoder rate adaptor unit (TRAU), the only delay that can be manipulated is the processing delay. The TRAUs are generally positioned remote to the base transceiver station (BTS). The channel codec units (CCUs) are located in the BTS. In general, 16 kbit/s traffic channels can be used for full rate speech between the TRAU and BTS. By putting the TRAU remote to the BTS, DSPs for speech coding can be utilized more efficiently to cut system cost. High performance DSPs, such as the Lucent DSP16000, can be used to further cut the cost per speech channel. This article presents an implementation of GSM enhanced full rate (EFR) codec on the Lucent Technologies' DSP16000. The original European Telecommunications Standards Institute (ETSI) C code has been restructured to address the issues of MIPS (million instructions per second), RAM usage, and processing delay. We give a performance overview of vocoder implementations on some existing fixed-point DSPs and discuss the architecture of the DSP16000. Details on how the ETSI C code is restructured are presented. The DSP16210 implementation results are then discussed.

High-performance DSPs

A digital signal processor (DSP) with programmable correlator array architecture is presented for third generation wireless communication system. The programmable correlator array can be reconfigured. as a chip match filter, code group detector, scrambling code detector, and RAKE receiver with low power consideration. The architecture and instruction set of the proposed DSP are specially designed for several key operations of wireless communications, such as channel estimation for RAKE combining, Viterbi algorithm and finite-impulse response filtering. The proposed DSP outperforms other previously presented communication digital signal processors in terms of several crucial operations of wireless applications. A chip of the proposed DSP was implemented using hybrid design method where the timing critical components were full-custom designed and the other parts were cell-based designed under TSMC 0.35-/spl mu/m CMOS 1P4M technology. We believe that the proposed system architecture would be useful for upcoming 3G mobile terminal applications.

https://video.ee.ntu.edu.tw/publication/paper/[J][2001][TCAS2][Chi-Kuang.Chen][1].pdf

A digital signal processor with programmable correlator array architecture for third generation wireless communication system

An implementation of GSM EFR using traditional single MAC DSPs (DSP1600) takes 24 MIPS to run a single speech channel. Lucent DSP16000 is a dual MAC high performance DSP. Analysis has shown DSP16000 code can run GSM EFR at 10 MIPS per channel with the same program space as DSP1600. The code has been re-structured to minimize the delays and RAM usage for multi-channel transcoder/rate adapter units (TRAU) applications. For a 100 MIPS DSP16210 running 6 EFR speech channels, DSP16210 code takes 15.7 K words of RAM with 3.2 ms maximum delay for the encoder and 0.5 ms for the decoder. Without re-structuring, the numbers are 27 K, 15.4 ms and 1.5 ms respectively. This makes the DSP16000 very attractive for TRAU applications. The initial implementation runs at 12.8 MIPS per channel with 19.3 K words of RAM, 4.7 ms maximum encoding delay and 0.5 ms maximum decoding delay for 6 speech channels.

T. Hollenbach

Papers

High-performance DSPs

GSM EFR implementation for TRAU application on DSP16000