High electric fields, that are characteristic of sub‐micron devices, produce highly energetic electrons, lack of equilibrium between electrons, optical phonons, and acoustic phonons, and high rates of heat generation. A simple coupled thermal and electrical model is developed for sub‐micron silicon semiconductor devices consisting of the hydrodynamic equations for electron transport and energy conservation equations for different phonon modes. An electron Reynolds number is proposed and used to simplify the electron momentum equation. On a case study of the metal‐oxide‐semiconductor field‐effect transistor with 0.24 μm gate length, the calculated transconductance of 0.175 1/Ω m agreed well with measured value of 0.180 1/Ω m at 2 V drain voltage. The maximum electron temperature is found to occur under the drain side of the gate where the electric field is the highest. Comparison with experimental data shows the predictions of optical and acoustic phonon temperature distributions to have the correct trend and the observed asymmetric behavior. Increase in substrate boundary temperature by 100 °C reduces the drain current by 17% and decreases the maximum electron temperature by 8%. The first effect increases device delay and the second effect decreases the possibility of device degradation by charge trapping in the gate oxide.

Concurrent thermal and electrical modeling of sub‐micrometer silicon devices

This work characterizes the temperature, channel length, and voltage dependences of substrate current, and presents a local model describing this behavior using Shockley's lucky electron (LE) model as a basis. For n-channel (p-channel) devices, the model is extended using a Maxwell-Boltzmann (MB) distribution of hot-electron (hole) energies above (below) the conduction (valence) band minimum (maximum). The model has been implemented in CADDET, a 2-D device simulator, and is able to explain all of the important features of substrate current which have been reported to date. The model is discussed in the context of works which look at both the local and physical nature of the impact ionization phenomenon. Based on this discussion, the model's parameters are shown to have a solid physical basis, requiring no reliance on curve fitting. The agreement between data and simulations thus enhances physical understanding of substrate current in MOSFET's, and warrants confident design of CMOS technologies for cryogenic operation.

Substrate current at cryogenic temperatures: Measurements and a two-dimensional model for CMOS technology

The effect of localized damage (interface states and/or trapped charges) on the ohmic region characteristics of electrically stressed MOSFET's is analyzed using the two-dimensional (2-D) solution of Poisson's equation. The device aging induced by hot-electron injection is summarized in the formation of a narrow defective interface region whose nature, extension, and position in the channel are the parameters of our investigation. Fundamental differences are observed between the effect of interface states and that of fixed oxide charges. In addition, the channel conductance G is shown to be greatly influenced by the extension and position of the zone of defects. The correlation between the degradation of the maximum transconductance and that of the threshold voltage is modeled and demonstrated to be an important tool in the diagnosis of device degradation. The interaction between the damaged and undamaged channel regions is found to produce a transconductance overshoot that attenuates the aging effects. A negative transconductance degradation (i.e., transconductance increase) in the case of positively charged defects and an apparent amelioration of the mobility degradation factor θ in the case of localized acceptor states are two direct consequences of this effect. The errors arising from the modeling of aged devices with 1-D homogeneous analytical models are outlined.

Two-dimensional modeling of locally damaged short-channel MOSFET's operating in the linear region

An analysis of the degradation of 1- mu m-gate-length nMOSFET operating under normal biasing conditions at room temperature is reported. A physical model of hot-electron trapping in SiO/sub 2/ is developed and is used with a two-dimensional device simulator (PISCES) to simulate the aging of the device under normal biasing conditions. The initial degradation takes place near the high-field drain region and spreads over a long time toward the source. The degraded I-V characteristics of the MOSFET exhibit a shift of the pinchoff voltage and a compression of the transconductance, for forward and reverse operation, respectively. The simulated degradation qualitatively agrees with reported experimental data. Large shifts of the MOSFET threshold voltage for small drain voltages result as the degradation is spreading toward the source. An inflection point arises for low gate and drain voltages in the drain I-V characteristics of the MOSFET. This inflection point originates when the pinchoff of the channel-induced trapped-electron charge is overcome by the drain voltage; the drain acts as a second gate (short-channel effect). The estimation of the device's lifetime by simulated aging is proposed. >

Simulation of hot-electron trapping and aging of nMOSFETs

Hot-electron-induced degradation in n-channel Si MOSFET's as a result of stress voltages applied at 77 K was studied. The devices were stressed at 77 K for 48 h with a drain voltage of 5 V and a gate voltage corresponding to that at which maximum substrate current was measured. Comparison of pre-stress and post-stress electrical characteristics for forward and for inverse mode operation at room temperature and at 77 K indicate that the observed degradation was due to the generation of hot-electron-induced acceptor interface states at the drain end of the device approximately 0.09 eV below the Si conduction band edge. No trapped charge resulting from hot-electron injection into the gate oxide was observed. The charge associated with the filled interface states had no observable effect on effective channel electron mobility at room temperature, and reduced that at 77 K by no more than 25 percent of the pre-stress value. Operation of CMOS inverters in either logic state (OFF, ON) resulted in no degradation of either device. Operation in a switching mode at 77 K did result in degradation of the n-channel device but not the p-channel FET. The observed degradation is thought to be correlated with the substrate current generated during the switching transient.

Hot-electron-induced interface state generation in n-channel MOSFET's at 77 K

Hot-electron-induced degradation of transconductance and of threshold voltage at 77 K of n-channel enhancement metal-gate MOSFET's was investigated as a function of electrical stress applied at liquid nitrogen temperature. After stress, the threshold voltage was found to have increased at low drain voltages but to have remained unchanged at higher drain voltages, and the saturation transconductance was virtually unchanged for operation in the normal mode. For operation in the inverse mode (source and drain interchanged), the threshold voltage was found to have increased, independent of drain voltage, while the saturation transconductance was decreased. The threshold voltage for inverted operation increased monotonically with stress time, while the saturation transconductance decreased initially and then saturated. This saturation corresponds to an order of magnitude decrease in carrier mobility in the channel near the drain. These results are interpreted using a model in which the threshold voltage and channel mobility are position-dependent. While hot-electron-induced degradation may not be a problem for devices operated only in the forward saturation region, it could be a serious problem for devices such as bilateral switches.

T.L. Honan

Papers

Hot-electron-induced degradation in MOSFET's at 77 K