Building on nearly two decades of reported results for MOSFET's fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFET's in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.

Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline Silicon

A 64 Mw*1 b/16 Mw*4 b DRAM with 30-ns access time which uses a double-metal layer and 0.4- mu m CMOS technology is reported. The external power supply is 3 V, while memory cell arrays operate at 2.2 V. Key circuits for the 64-Mb DRAM are (1) a latched-sense, shared-sense circuit with open bit-line read-out and folded bit-line rewrite operations (LOF) to reduce inter-bit-line coupling noise, (2) alternatively activated and separately end-located word drivers and X decoders to reduce word-line selection delay, and (3) built-in self test and repair circuits using spare memory cells to reduce test costs and increase chip reliability. >

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Semiconductor memory device.

The memory cell and technology requirements and issues for 64- and 256-Mb MOS DRAMs (dynamic random-access memories) based on the charge storage concept (one-transistor cell) are analyzed. Projected requirements have been developed for key parameters such as die size, cell area, charge capacity, storage capacitance and area, leakage current, and on-current. These requirements are based on an analysis and assessment of expected improvements in soft error rate, sense amplifier sensitivity, 0-1 storage voltage difference, and bit line capacitance. Pivotal issues specific to the DRAM are identified. It is concluded that sufficient progress will be made so that 64-Mb DRAMs will be successfully produced in the early to mid-1990s. >

Memory cell and technology issues for 64- and 256-Mbit one-transistor cell MOSD DRAMs

Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon

CIRCUIT TECHNIQUES developed for a stacked capacitor 256Kb NMOS DRAM test model to achieve the best use of a small cell ( 3 8 . 2 5 ~ 2 ) used as a storage element will be reported. In the development of next generation DRAMs, a certain storage capacitance value (approximately 50fF) must be assembled in the small cell area with minimal capture rate of minority carriers in the substrate. Conventional double polysilicon cells are becoming obsolete for these requirements. Among several improved cell structures, the stacked capacitor cell’ affords larger storage capacitance by extending the storage region onto the transfer gate. The use of capacitive-coupled bit lines (CCB) in triple polysilicon cell structures are similar, but have an approximately 1.5 times larger storage area, because the total cell area is utilized for the capacitor. Figure 1 shows a plane and cross sectional view of the cell. A large storage area was created by reciprocally connecting the transfer-gate and the capacitor. This has eliminated the space for a contact hole between bit line to cell. The cell output voltage of CCB and standard metal bit line structures were compared: Figure 2 shows the calculated output voltage as a function of cell size. Lateral dimensions including storage capacitors were assumed to vary with cell size, while the spacing between capacitors and the metal bit line width were kept constant because the minimum line width and the spacing were assumed. Vertical dimensions were also kept constant. A two-dimensional numerical analysis method was used for capacitance evaluation, and the effects of capacitance between adjacent bit lines were taken into account. Since the bit line width of CCB structures varies with cell size, the parasitic capacitance is comparably large for cell sizes over 4 0 m 2 and the output voltage is lower than that for metal bit line structure. But if the memory cells are very small, the situation is reversed; the capacitance of metal bit lines does not reduce much with cell size due to fringe Capacitance components and the emergence of capacitance between bit lines, while the capacitor area rapidly decreases. For the same output voltages, a CCB cell with larger storage capacitance is more resistive to soft errors and superior performance is expected from very small cells. The cell’s operational biases are slightly different from conventional cells. In write operations, bit lines are set at the V,, or Vss level according to the data being written. The voltage source lines provide a Vcc level to each storage node __

A capacitance coupled bit line cell for Mb level DRAMs

A 38-/spl mu/m/sup 2/ dynamic random-access memory (dRAM) cell with a capacitance-coupled bit line (CCB) approach is described. This cell enables a storage capacitor area 2-2.5 times larger than double polysilicon-type cells, or half the cell area with the same design rules. Memory operation with this cell is explained and the bit line stray capacitance is analyzed using a two-dimensional numerical calculation method. The cell output voltage is compared with those of other cells, taking the capacitance between bit lines into account. An experimental 256K dRAM was built for testing, and operated successfully.

A Capacitance-Coupled Bit Line Cell

A 38-µm2dynamic random-access memory (dRAM) cell with a capacitance-coupled bit line (CCB) approach is described. This cell enables a storage capacitor area 2-2.5 times larger than double polysilicon-type cells, or half the cell area with the same design rules. Memory operation with this cell is explained and the bit line stray capacitance is analyzed using a two-dimensional numerical calculation method. The cell output voltage is compared with those of other cells, taking the capacitance between bit lines into account. An experimental 256K dRAM was built for testing, and operated successfully.

T. Nakamura

Papers

A capacitance coupled bit line cell for Mb level DRAMs

A Capacitance-Coupled Bit Line Cell

A capacitance-coupled bit line cell