A low-temperature sintering technique enabled by a nanoscale silver paste has been developed for attaching large-area (>100 mm2) semiconductor chips. This development addresses the need of power device or module manufacturers who face the challenge of replacing lead-based or lead-free solders for high-temperature applications. The solder-reflow technique for attaching large chips in power electronics poses serious concern on reliability at higher junction temperatures above 125°C. Unlike the soldering process that relies on melting and solidification of solder alloys, the low-temperature sintering technique forms the joints by solid-state atomic diffusion at processing temperatures below 275°C with the sintered joints having the melting temperature of silver at 961°C. Recently, we showed that a nanoscale silver paste could be used to bond small chips at temperatures similar to soldering temperatures without any externally applied pressure. In this paper, we extend the use of the nanomaterial to attach large chips by introducing a low pressure up to 5 MPa during the densification stage. Attachment of large chips to substrates with silver, gold, and copper metallization is demonstrated. Analyses of the sintered joints by scanning acoustic imaging and electron microscopy showed that the attachment layer had a uniform microstructure with micrometer-sized porosity with the potential for high reliability under high-temperature applications.

Low-Temperature Sintering of Nanoscale Silver Paste for Attaching Large-Area $({>}100~{\rm mm}^{2})$ Chips

This paper investigates the switching behavior of normally OFF silicon carbide (SiC) JFETs in an inverter for a motor drive. The parasitic ringing caused by different parasitic effects is analyzed. Two different methods, the use of an RC snubber and the use of suppression ferrite component, are investigated for dampening the parasitic oscillations. It is found that applying a ferrite bead not only dampens the parasitic oscillations, but also results in significantly lower switching losses. Furthermore, it is shown that the capacitive coupling between SiC devices in the bridge leg and heat sinks significantly deteriorates the JFETs' switching performance. The effect of two substrates, an insulated metal substrate and a printed circuit board, on the capacitive coupling is investigated. A method in which the use of two separate heat spreaders minimizes the capacitive coupling, thus, exploiting the full potential of fast SiC JFETs is proposed.

Improving SiC JFET Switching Behavior Under Influence of Circuit Parasitics

This paper presents a systematic evaluation approach of three-phase pulsewidth-modulated (PWM) AC-AC converter topologies for high-density applications. All major components and subsystems in a converter are considered and the interdependence of all the constraints and design parameters is systematically studied. The key design parameters, including switching frequency, modulation scheme, and passive values, are selected by considering their impacts on loss, harmonics, electromagnetic interference (EMI), control dynamics and stability, and protection. The component selection criteria as well as the physical design procedures are developed from the high-density standpoint. The concept of using the same inductor for harmonic suppression and EMI filtering is introduced in the design. With the proposed methodology, four converter topologies, a back-to-back voltage source converter (BTB-VSC), a nonregenerative three-level boost (Vienna-type) rectifier plus voltage source inverter (NTR-VSI), a back-to-back current source converter (BTB-CSC), and a 12-switch matrix converter, are analyzed and compared for high specific power using SiC devices. The evaluation results show that with the conditions specified in this paper, BTB-VSC and NTR-VSI have considerably lower loss, resulting in higher specific power than BTB-CSC and the matrix converter. The proposed methodology can be applied to other topologies with different comparison metrics and can be a useful tool for high-density topology selection.

A Systematic Topology Evaluation Methodology for High-Density Three-Phase PWM AC-AC Converters

Characterization and Modeling of High-Switching-Speed Behavior of SiC Active Devices

This paper studies the possibility of building a Modular Multilevel Converter (M2C) using Silicon Carbide (SiC) switches. The main focus is on a theoretical investigation of the conduction losses of such a converter and a comparison to a corresponding converter with silicon insulated gate bipolar transistors. Both SiC BJTs and JFETs are considered and compared in order to choose the most suitable technology. One of the sub-modules of a down-scaled 10 kVA prototype M2C is replaced with a sub-module with SiC JFETs without anti-parallel diodes. It is shown that diode-less operation is possible with the JFETs conducting in the negative direction, leaving the possibility to use the body diode during the switching transients. Experimental waveforms for the SiC sub-module verify the feasibility during normal steady-state operation. The loss estimation shows that a 300 MW M2C for high-voltage direct current transmission would potentially have an efficiency of approximately 99,8 % if equipped with future 3.3 kV 1.2 kA SiC JFETs.

http://kth.diva-portal.org/smash/get/diva2:467521/FULLTEXT02.pdf

High-power modular multilevel converters with SiC JFETs

This paper presents the switching characterization of 1200 V, 5 A SiC JFET prototype devices for application in an AC three-phase current-source rectifier (CSR) with a switching frequency of 150 kHz. The result of device on-resistance is shown as a function of junction temperature. Using a simplified gate drive design, the switching characteristics of the SiC JFET are measured experimentally at voltage levels up to 600 V, current up to 5 A, junction temperature up to 200 °C, and varying gate resistance. From these measurements, the switching times and energies are calculated and plotted for various conditions. Finally, the application of the SiC JFET in the CSR is discussed, and conduction and switching losses are calculated. Results show that the SiC JFET provides low switching loss, even at high switching frequencies.

Evaluation of SiC JFETs for a Three-Phase Current-Source Rectifier with High Switching Frequency

Power electronics products, to date, are essentially custom-designed and manufactured using non-standard parts. The products cycle times are long and manufacturing processes are labor-intensive, thus, resulting in poor reliability and high cost. The Center for Power Electronics Systems, established in 1998 as one of the National Science Foundation Engineering Research Centers, is charged in leading the nation in the development of an integrated power electronics system approach via integrated power electronics modules (IPEMs). A brief discussion of the center's research enterprise and strategic plan in addressing key technological areas and advancements needed to improve the characteristics of power electronics systems, such as increased levels of integration, standardization of parts and improved packaging techniques for enhanced thermal management and electrical performances. The technologies being developed for the realization of integrated systems include planar metallization to allow three-dimensional structural integration of power devices and control functions, integration of power passives, integration of RF and EMI filters, and integration of electrical/thermal design tools.

IPEM-Based Power Electronics System Integration

In this paper, we present a novel die-attach solution based on low-temperature sintering of nanosilver paste for high-temperature operation of SiC power devices. The nanosilver paste was prepared by mixing silver nanoparticles with an organic binder system. SiC Schottky diodes were die-attached onto direct-bond-copper (DBC) substrates using the stencil- or screen-printed nanosilver paste layers with thickness 1~2 mil. After holding at 300deg C for about 40 minutes to burn out all the organic components, the nanosilver paste consolidated into strong and uniform die-attach bonding with either silver- or gold-coated DBC substrates. Then, the silver die-attached SiC devices were cooled down to room temperature and their top terminals were gold wire-bonded for fulfilment of the high-temperature power packages. Finally the interconnected SiC devices were heated up from room temperature to the highest toleration points of the devices for the high-temperature operation and characterization. Results of the measurements demonstrated that the low-temperature sintering technique is an effective die-attach solution for high-temperature electronics.

T. Paul Chow

Papers

Evaluation of SiC JFETs for a Three-Phase Current-Source Rectifier with High Switching Frequency

IPEM-Based Power Electronics System Integration

Low-Temperature Sintered Silver Attachment for High-Temperature Operation of SiC Power Devices