Intermodulation distortion in field-effect transistors (FETs) at RF frequencies is analyzed using the Volterra-series analysis. The degrading effect of the circuit reactances on the maximum IIP3 in the conventional derivative-superposition (DS) method is explained. The noise performance of this method is also analyzed and the effect of the subthreshold biasing of one of the FETs on the noise figure (NF) is shown. A modified DS method is proposed to increase the maximum IIP3 at RF. It was used in a 0.25-mum Si CMOS low-noise amplifier (LNA) designed for cellular code-division multiple-access receivers. The LNA achieved +22-dBm IIP3 with 15.5-dB gain, 1.65-dB NF, and 9.3 mA@2.6-V power consumption

Modified derivative superposition method for linearizing FET low noise amplifiers

A broadband inductorless low-noise amplifier (LNA) design that utilizes simultaneous noise and distortion cancellation is presented. Concurrent cancellation of the intrinsic third-order distortion from individual stages is exhibited with the common-gate and common-source cascade. The LNA is then limited by the second-order interaction between the common source and common gate stages, which is common in all cascade amplifiers. Further removal of this third-order distortion is achieved by incorporating a second-order-distortion-free circuit technique in the common gate stage. Implemented in 0.13 m CMOS technology, this LNA achieved 16 dBm in both the 900 MHz and 2 GHz bands. Measurements demonstrate that the LNA has a minimum internal gain of 14.5 dB, noise figure of 2.6 dB from 800 MHz to 2.1GHz while drawing 11.6 mA from 1.5 V supply voltage.

A Highly Linear Broadband CMOS LNA Employing Noise and Distortion Cancellation

Highly linear receiver RF front-end adopting MOSFET transconductance linearization by linearly superposing several common-source FET transistors in parallel (multiple gated transistor, or MGTR), combined with some additional circuit techniques are reported. In MGTR circuitry, linearity is improved by using transconductance linearization which can be achieved by canceling the negative peak value of g/sub m/'' of the main transistor with the positive one in the auxiliary transistor having a different size and gate drive combined in parallel. This enhancement, however, is limited by the distortion originated from the combined influence of g/sub m/' and harmonic feedback, which can greatly be reduced by the cascoding MGTR output for the amplifier and by the tuned load for the mixer. Experimental results designed using the above techniques show IIP/sub 3/ improvements at given power consumption by as much as 10 dB for CMOS low-noise amplifier at 900 MHz and 7 dB for Gilbert cell mixer at 2.4 GHz without sacrificing other features such as gain and noise figure.

Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors

A transformer-feedback voltage-controlled oscillator (TF-VCO) is proposed to achieve low-phase-noise and low-power designs even at a supply below the threshold voltage. The advantages of the proposed TF-VCO are described together with its detailed analysis and its cyclo-stationary characteristic. Two prototypes using the proposed TF-VCO techniques are demonstrated in a standard 0.18-/spl mu/m CMOS process. The first design using two single-ended transformers is operated at 1.4 GHz at a 0.35-V supply using PMOS transistors whose threshold voltage is around 0.52 V. The power consumption is 1.46 mW while the measured phase noise is -128.6 dBc/Hz at 1-MHz frequency offset. Using an optimum differential transformer to maximize quality factor and to minimize the chip area, the second design is operated at 3.8 GHz at a 0.5-V supply with power consumption of 570 /spl mu/W and a measured phase noise of -119 dBc/Hz at 1-MHz frequency offset. The figures of merits are comparable or better to that of other state-of-the-art VCO designs operating at much higher supply voltage.

Ultra-low-Voltage high-performance CMOS VCOs using transformer feedback

This work proposes a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, and analyzes its performance with Volterra series. The linearization technique is applied to an ultra-wideband (UWB) cascode common gate Low Noise Amplifier (CG-LNA), and two additional reference designs are implemented to evaluate the linearization technique - a standard (without linearization) cascode CG-LNA and a single-transistor CG-LNA. The single-transistor CG-LNA achieves +6.5 to +9.5 dBm IIP3, 10 dB (max.) gain, and 2.9 dB (min.) NF over a 3-11 GHz bandwidth (BW); the LNA consumes 2.4 mW from a 1.3 V supply. The cascode linearized LNA achieves +11.7 to +14.1 dBm IIP3, 11.6 dB (max.) gain, and 3.6 dB (min.) NF over 1.5 to 8.1 GHz; the cascode LNA consumes 2.62 mW from a 1.3 V supply. Experimental results show that the linearization technique improves the cascode LNA's IIP3 by a factor of 3.5 to 9 dB over a 2.5-10 GHz frequency range.

A Low-Power, Linearized, Ultra-Wideband LNA Design Technique

An experimental 2.4-GHz CMOS radio composed of RF and digital circuits for the low-power and low-rate preliminary IEEE802.15.4 WPAN is reported, consuming 21 mW in receive mode and 30 mW in transmit mode. The RF design focus is to maximize linearity for a given power consumption using linearization methods which lead an order of magnitude improvement in LNA/mixer IIP3/power performance. Chip-on-PCB technology allows implementation of a coin-sized radio at very low cost, which also provides 3 dBi gain patch antenna and high Q (>50) inductors.

An experimental coin-sized radio for extremely low-power WPAN (IEEE 802.15.4) application at 2.4 GHz

A CMOS RF digitally programmable gain amplifier, covering various terrestrial mobile digital TV standards (DMB, ISDB-T, and DVB-H) is implemented. 13 dB IIP3 improvement is attained without losing out on other performance criteria like gain, NF, CMRR, etc. at similar power consumption. This is achieved by applying a newly proposed differential circuit gm" cancellation technique. The IC exhibits 55 dB gain range with 0.25 dB resolution, 4.5 dB NF; a -4 dBm IIP3 (maximum 30 dBm) and 25 dB gain at 16mW power consumption.

A 13 dB IIP3 improved low-power CMOS RF programmable gain amplifier using differential circuit transconductance linearization for various terrestrial mobile D-TV applications

A highly linear CMOS RF amplifier and mixer circuits adopting MOSFET transconductance linearization by linearly superposing several common-source FET transistors in parallel, combined with some additional circuit techniques such as cascode for amplifier and harmonic tuning for mixer, are reported. Experimental result designed using above techniques shows IP3 improvements at given power consumption by as large as 10 dB for RF amplifier at 900 MHz and 7 dB for Gilbert cell mixer at 2.4 GHz without sacrificing other features such as gain and NF.

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Highly linear RF CMOS amplifier and mixer adopting MOSFET transconductance linearization by multiple gated transistors

The present invention is related to a variable gain low noise amplifier that optimizes input matching, gain and noise characteristics, and linearity. The variable gain low noise amplifier according to an embodiment of the present invention includes a first amplifying cell that operates in a high gain mode, a second amplifying cell that operates in a low gain mode, a selectively matching circuit, and a first short-circuit means. The variable gain low noise amplifier according to the present invention selects the best operation in each gain mode so that the circuit operated in high and low gain modes does not affect a load of another circuit.

Tae Wook Kim

Papers

Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors

An experimental coin-sized radio for extremely low-power WPAN (IEEE 802.15.4) application at 2.4 GHz

A 13 dB IIP3 improved low-power CMOS RF programmable gain amplifier using differential circuit transconductance linearization for various terrestrial mobile D-TV applications

Highly linear RF CMOS amplifier and mixer adopting MOSFET transconductance linearization by multiple gated transistors

Variable gain low noise amplifier