We describe a Fan-Out Wafer-Level Packaging (FOWLP) integration process that is used to build an extremely flexible heterogeneous integration platform called "FlexTrateTM". We integrated a daisy chain connected 10×20 array of 1 mm2 Si dies over a 35 mm × 18 mm area using vertically corrugated Cu interconnects of 40 µm pitch and ~5 µm thickness. The system is reliable even upon bending to 1 mm bending radius for over 1000 bending cycles. We demonstrate a 37 mm × 52 mm foldable display with 1 mm2 InGaN LEDs using this technology. Cyclic mechanical bending (1 mm bending radius), optical, and thermal reliability of integrated display are investigated.

Heterogeneous Integration of a Fan-Out Wafer-Level Packaging Based Foldable Display on Elastomeric Substrate

We fabricate FlexTrateTM that is highly integrated bendable and/or rollable electronic systems in which various Si and/or III–V chips are embedded in elastomers and interconnected at the wafer level. This paper describes the process integration of the FlexTrateTM using massively parallel capillary self-assembly and a new single stress buffer layer technologies to form fine-pitch interconnection between the embedded neighboring chips and characterize the electrical/mechanical properties.

Tak Fukushima

Papers

Process Integration for FlexTrate TM