Amir Hanna

TL;DR: In this article, a flexible version of traditional thin lead zirconium titanate ((Pb1.1Zr0.48Ti0.52O3)-based ferroelectric random access memory (FeRAM) on silicon shows record performance in flexible arena.

TL;DR: Through the use of inner/outer core-shell gates, a single III-V hetero-structured nanotube TFET leverages physically larger tunneling area while achieving higher driver current (ION) and saving real estates by eliminating arraying requirement.

TL;DR: In this article, the authors focus on geography-specific optimization of ground-mounted vertical bifacial solar farms for the entire world, where they consider the effects of direct, diffuse, and albedo light.

Abstract: We discuss the physics of conventional channel material (silicon/germanium hetero-structure) based transistor topology mainly core/shell (inner/outer) gated nanotube vs. gate-all-around nanowire architecture for tunnel field effect transistor application. We show that nanotube topology can result in higher performance through higher normalized current when compared to nanowire architecture at Vdd = 1 V due to the availability of larger tunneling cross section and lower Shockley-Reed-Hall recombination. Both architectures are able to achieve sub 60 mV/dec performance for more than five orders of magnitude of drain current. This enables the nanotube configuration achieving performance same as the nanowire architecture even when Vdd is scaled down to 0.5 V.

TL;DR: In this paper, a scalable flexible hybrid electronics based on a novel fan-out wafer-level packaging (FOWLP) methodology is presented, where small dielets are embedded in flexible substrates called FlexTrate.