The interest in nanoscale materials stems from the fact that new properties are acquired at this length scale and, equally important, that these properties * To whom correspondence should be addressed. Phone, 404-8940292; fax, 404-894-0294; e-mail, mostafa.el-sayed@ chemistry.gatech.edu. † Case Western Reserve UniversitysMillis 2258. ‡ Phone, 216-368-5918; fax, 216-368-3006; e-mail, burda@case.edu. § Georgia Institute of Technology. 1025 Chem. Rev. 2005, 105, 1025−1102

Chemistry and properties of nanocrystals of different shapes.

We present a comprehensive, up-to-date compilation of band parameters for the technologically important III–V zinc blende and wurtzite compound semiconductors: GaAs, GaSb, GaP, GaN, AlAs, AlSb, AlP, AlN, InAs, InSb, InP, and InN, along with their ternary and quaternary alloys. Based on a review of the existing literature, complete and consistent parameter sets are given for all materials. Emphasizing the quantities required for band structure calculations, we tabulate the direct and indirect energy gaps, spin-orbit, and crystal-field splittings, alloy bowing parameters, effective masses for electrons, heavy, light, and split-off holes, Luttinger parameters, interband momentum matrix elements, and deformation potentials, including temperature and alloy-composition dependences where available. Heterostructure band offsets are also given, on an absolute scale that allows any material to be aligned relative to any other.

Band parameters for III–V compound semiconductors and their alloys

The term photonic crystals appears because of the analogy between electron waves in crystals and the light waves in artificial periodic dielectric structures. During the recent years the investigation of one-, two-and three-dimensional periodic structures has attracted a widespread attention of the world optics community because of great potentiality of such structures in advanced applied optical fields. The interest in periodic structures has been stimulated by the fast development of semiconductor technology that now allows the fabrication of artificial structures, whose period is comparable with the wavelength of light in the visible and infrared ranges.

http://ieeexplore.ieee.org/iel5/6354/16969/00781867.pdf

Photonic crystals

The compelling demand for higher performance and lower power consumption in electronic systems is the main driving force of the electronics industry's quest for devices and/or architectures based on new materials. Here, we provide a review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches. We focus on the performance limits and advantages of these materials and associated technologies, when exploited for both digital and analog applications, focusing on the main figures of merit needed to meet industry requirements. We also discuss the use of two-dimensional materials as an enabling factor for flexible electronics and provide our perspectives on future developments.

Electronics based on two-dimensional materials

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

The fabrication of transistors using vertical, six-sided core–multishell indium gallium arsenide nanowires with an all-surrounding gate on a silicon substrate combines the advantages of a three-dimensional gate architecture with the high electron mobility of the III–V nanowires, drastically enhancing the on-state current and transconductance. In the continuing drive to improve and miniaturize transistors, the microelectronics industry has recently adopted three-dimensional electronic gate structures. Another way of improving transistors is to use semiconductor materials with higher electron mobility than silicon, although this presents significant fabrication challenges. Katsuhiro Tomioka et al. combine the two approaches; they grow, with high precision, vertical, six-sided core–multishell indium gallium arsenide nanowires with an all-surrounding gate on a silicon substrate. The resulting devices demonstrate superior transistor performance with excellent on/off switching behaviour and fast operation. Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years’ time1,2,3,4. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III–V materials, specifically InGaAs, are being explored as alternative fast channels on silicon5,6,7,8,9 because of their high electron mobility and high-quality interface with gate dielectrics10. The idea of surrounding-gate transistors11, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated12,13 because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core–multishell nanowires as channels. Surrounding-gate transistors using core–multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

A III–V nanowire channel on silicon for high-performance vertical transistors

We report on integration of GaAs nanowire-based light-emitting-diodes (NW-LEDs) on Si substrate by selective-area metalorganic vapor phase epitaxy. The vertically aligned GaAs/AlGaAs core-multishell nanowires with radial p-n junction and NW-LED array were directly fabricated on Si. The threshold current for electroluminescence (EL) was 0.5 mA (current density was approximately 0.4 A/cm2), and the EL intensity superlinearly increased with increasing current injections indicating superluminescence behavior. The technology described in this letter could help open new possibilities for monolithic- and on-chip integration of III−V NWs on Si.

GaAs/AlGaAs Core Multishell Nanowire-Based Light-Emitting Diodes on Si

We report on control of growth directions of InAs nanowires on Si substrate. We achieved to integrate vertical InAs nanowires on Si by modifying initial Si(111) surface in selective-area metal-organic vapor phase epitaxy with flow-rate modulation mode at low temperature. Cross-sectional transmission electron microscope and Raman scattering showed that misfit dislocation with local strains were accommodated in the interface.

Control of InAs Nanowire Growth Directions on Si

We report on the fabrication of GaAs hexagonal nanowires surrounded by {110} vertical facets on a GaAs (111) B substrate using selective-area (SA) metalorganic vapor-phase epitaxial (MOVPE) growth. The substrate for SA growth was partially covered with thin SiO2, and a circular mask opening with a diameter d0 of 50–200 nm was defined. After SA-MOVPE, GaAs nanowires with a typical diameter d ranging from 50 to 200 nm and a height from 2 to 9μm were formed vertically on the substrate without any catalysts. The size of the nanowire depends on the growth conditions and the opening size of the masked substrate. A possible growth mechanism is also discussed.

/pdf/catalyst-free-growth-of-gaas-nanowires-by-selective-area-13i628hwjd.pdf

Catalyst-free growth of GaAs nanowires by selective-area metalorganic vapor-phase epitaxy

Highly uniform GaAs/GaAsP coaxial nanowires were prepared via selective-area metal organic vapor phase epitaxy. Photoluminescence spectra from a single nanowire indicate that the obtained heterostructures can produce near-infrared (NIR) lasing under pulsed light excitation. The end facets of a single nanowire form a natural mirror surface to create an axial cavity, which realizes resonance and give stimulated emission. This study is a considerable advance toward the realization of nanowire-based NIR light sources.

Takashi Fukui

Papers

A III–V nanowire channel on silicon for high-performance vertical transistors

GaAs/AlGaAs Core Multishell Nanowire-Based Light-Emitting Diodes on Si

Control of InAs Nanowire Growth Directions on Si

Catalyst-free growth of GaAs nanowires by selective-area metalorganic vapor-phase epitaxy

Single GaAs/GaAsP coaxial core-shell nanowire lasers.