This paper summarizes the current state of the art and recent trends in software engineering economics. It provides an overview of economic analysis techniques and their applicability to software engineering and management. It surveys the field of software cost estimation, including the major estimation techniques available, the state of the art in algorithmic cost models, and the outstanding research issues in software cost estimation.

Software engineering economics

R.E. Bryant proposed a method to handle logic expressions (IEEE Trans. Comp., vol.25, no.8, p.667-91, 1986) which is based on binary decision diagrams (BDD) with restriction; variable ordering ix fixed throughout a diagram. The method is more efficient than other methods proposed so far and depends heavily on variable ordering. A simple but powerful algorithm for variable ordering is developed. The algorithm tries to find a variable ordering which minimizes the number of crosspoints of nets when the circuit diagram is drawn. This is applied to the Boolean comparison of ISCAS benchmark circuits for test pattern generation. The results show that binary decision diagrams (BDD) with the proposed ordering method can verify almost all benchmark circuits in less than several central processor unit (CPU) minutes, which is one hundred times (or more) faster than times reported in the literature. Some techniques for circuit evaluation ordering are also mentioned. >

Evaluation and improvement of Boolean comparison method based on binary decision diagrams

This paper presents SOCRATES, a system of programs which synthesize and optimize combinational logic circuits from boolean equations. SOCRATES optimizes logic using boolean and algebraic minimization techniques, and it optimizes circuits derived from this logic in a user defined technology with a rule based expert system. This paper discusses the goals of logic synthesis and the capabilities needed in a tool to meet these goals. SOCRATES's capabilities are then presented and demonstrated with experiments run on circuits from the 1986 Design Automation Conference synthesis benchmark set.

SOCRATES: A System for Automatically Synthesizing and Optimizing Combinational Logic

This article describes new concepts and algorithms used to generate tests for VLSI scan-design circuits. The new algorithms include: 1. a low-cost fault-independent algorithm (SMART), 2. a fault-oriented algorithm (FAST), and 3. an algorithm for dynamic test set compaction. The fault-oriented algorithm is guided by new controllability/observability cost functions whose objective is to minimize the amount of search done in test generation.

SMART And FAST: Test Generation for VLSI Scan-Design Circuits

Electronic Design Automation for Integrated Circuits Handbook

This paper describes a program which generates test patterns for scan design circuits with tri-state modules and bidirectional terminals. The test generation procedure uses a path sensitization technique with 14 signal values. The principal features of this program are test generation with automatic decision of I/O mode of bidirectional terminals, generation of test sets for high impedance state, and generation of test sets for system clock control circuits of shift register latches (SRLs) by using shift-in function of SRLs.

Test Generation for Scan Design Circuits with Tri-State Modules and Bidirectional Terminals

The outline and the application results of a computer aided logic design system which combines automatic translation of TTL SSI/MSI logic into gate array logic, human intervention, auxiliary logic simulation, and automatic documentation are described. Automatic translation of logic circuit is done by macro expansion technique coupled with redundant logic reduction procedures.

An Integrated Computer Aided Design System for Gate Array Masterslices: Part 1. Logic Reorganization System Lores-2

This paper describes a bus design rule checking method which efficiently checks whether signal conflicts may occur on the tri-state buses in a given circuit and whether the buses may be in floating states. By using BDD (binary decision diagram) representations, a practical bus design rule check program has been obtained.

Tri-state bus conflict checking method for ATPG using BDD

LORES-2 is a logic reorganization system which greatly contributes to the effective automation of logic design. LORES-2 uses a macro-expansion technique to help designers transform printed-circuit assembly logic composed of SSI and MSI circuits into master-slice LSI logic circuits. The number of gates of the most reorganized LSI circuit falls within ± 20 percent of the number of gates of the original circuit. When ROMS and/or PLAs are not-allowed on the target LSI circuit, those elements are converted into optimized, multilevel random logic using logic minimization, factoring and macro-expansion techniques.

LORES-2: A Logic Reorganization System

This paper deals with an LSI design management system which automates CAD program performance analysis. CAD program/library version control, design process control, design cost estimation and the collection of such statistical information as the sizes of the circuits being designed. The design management automation has been accomplished by analyzing statistical and control information generated by all the CAD programs and the operating system.

Takuji Ogihara

Papers

Test Generation for Scan Design Circuits with Tri-State Modules and Bidirectional Terminals

An Integrated Computer Aided Design System for Gate Array Masterslices: Part 1. Logic Reorganization System Lores-2

Tri-state bus conflict checking method for ATPG using BDD

LORES-2: A Logic Reorganization System

ASTA: LSI Design Management System